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Features
* Incorporates the ARM7TDMI(R) ARM(R) Thumb(R) Processor
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash - 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes - 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes - Single Cycle Access at Up to 30 MHz in Worst Case Conditions - Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed - Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms - 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit - Fast Flash Programming Interface for High Volume Production Internal High-speed SRAM, Single-cycle Access at Maximum Speed - 64 Kbytes (AT91SAM7X256) - 32 Kbytes (AT91SAM7X128) Memory Controller (MC) - Embedded Flash Controller, Abort Status and Misalignment Detection Reset Controller (RSTC) - Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector - Provides External Reset Signal Shaping and Reset Source Status Clock Generator (CKGR) - Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL Power Management Controller (PMC) - Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode - Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) - 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) - 12-bit key-protected Programmable Counter - Provides Reset or Interrupt Signals to the System - Counter May Be Stopped While the Processor is in Debug State or in Idle Mode Real-time Timer (RTT) - 32-bit Free-running Counter with Alarm - Runs Off the Internal RC Oscillator Two Parallel Input/Output Controllers (PIO) - Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
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AT91 ARM(R) Thumb(R)-based Microcontrollers AT91SAM7X256/ AT91SAM7X128 Preliminary
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* Seventeen Peripheral DMA Controller (PDC) Channels * One Advanced Encryption System (AES)
- 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications - Buffer Encryption/Decryption Capabilities with PDC One Triple Data Encryption System (TDES) - Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications - Optimized for Triple Data Encryption Capability One USB 2.0 Full Speed (12 Mbits per second) Device Port - On-chip Transceiver, 1352-byte Configurable Integrated FIFOs One Ethernet MAC 10/100 base-T - Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) - Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive One Part 2.0A and Part 2.0B Compliant CAN Controller - Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter One Synchronous Serial Controller (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Two Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support - Full Modem Line Support on USART1 Two Master/Slave Serial Peripheral Interfaces (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects One Three-channel 16-bit Timer/Counter (TC) - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit Power Width Modulation Controller (PWMC) One Two-wire Interface (TWI) - Master Mode Support Only, All Two-wire Atmel EEPROMs Supported One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os SAM-BATM Boot Assistance - Default Boot program - Interface with SAM-BA Graphic User Interface IEEE 1149.1 JTAG Boundary Scan on All Digital Pins 5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each Power Supplies - Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components - 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply - 1.8V VDDCORE Core Power Supply with Brownout Detector Fully Static Operation: Up to 55 MHz at 1.65V and 85 C Worst Case Conditions Available in a 100-lead LQFP Green Package
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1. Description
Atmel's AT91SAM7X256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 256/128 Kbyte high-speed Flash and 64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN controller, an AES 128 Encryption accelerator and a Triple Data Encryption System. A complete set of system functions minimizes the number of external components. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM7X256/128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of peripheral functions, including USART, SPI, CAN Controller, Ethernet MAC, AES 128 accelerator, TDES, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the AT91SAM7X256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring secure communication over, for example, Ethernet, CAN wired and Zigbee wireless networks.
2. Configuration Summary of the AT91SAM7X256 and AT91SAM7X128
The AT91SAM7X256 and AT91SAM7X128 differ only in memory sizes. Table 2-1 summarizes the configurations of the two devices.
Table 2-1.
Device AT91SAM7X256 AT91SAM7X128
Configuration Summary
Flash 256K bytes 128K bytes SRAM 64K bytes 32K bytes
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3. AT91SAM7X256/128 Block Diagram
Figure 3-1.
TDI TDO TMS TCK JTAGSEL
AT91SAM7X256/X128 Block Diagram
JTAG SCAN
ICE
ARM7TDMI Processor
1.8 V Voltage Regulator
VDDIN GND VDDOUT VDDCORE
TST FIQ
System Controller
AIC
PIO IRQ0-IRQ1
Memory Controller
PDC PDC
VDDIO
DRXD DTXD
DBGU
Embedded Flash Controller Abort Status
SRAM
64/32 Kbytes
Address Decoder Misalignment Detection
PCK0-PCK3 PLLRC XIN XOUT
VDDFLASH
PLL OSC RCOSC PMC Peripheral Bridge
Flash
256/128 Kbytes
ERASE
VDDCORE VDDFLASH VDDCORE NRST
BOD POR Reset Controller
Peripheral DMA Controller
17 Channels
ROM Fast Flash Programming Interface
PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1
PIT
APB
WDT RTT PIOA
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 RI1 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADVREF
SAM-BA
DMA FIFO Ethernet MAC 10/100
PDC
PIOB
USART0
PDC PDC FIFO
Transceiver
ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL, ECRSDV ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO EF100 VDDFLASH DDM DDP
USART1
USB Device
PIO
PDC PDC
PWMC
PDC
SPI0
PDC PDC
SSC
PDC
Timer Counter SPI1 TC0
PDC PDC
TC1 TC2
ADC
TWI
CAN
PDC
PWM0 PWM1 PWM2 PWM3 TF TK TD RD RK RF TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK CANRX CANTX
PIO
AES 128
PDC PDC
TDES
PDC
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PIO
AT91SAM7X256/128 Preliminary
4. Signal Description
Table 4-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL GND
Voltage Regulator and ADC Power Supply Input Voltage Regulator Output Flash and USB Power Supply I/O Lines Power Supply Core Power Supply PLL Ground
Power Power Power Power Power Power Ground
3V to 3.6V 1.85V 3V to 3.6V 3V to 3.6V 1.65V to 1.95V 1.65V to 1.95V
Clocks, Oscillators and PLLs XIN XOUT PLLRC PCK0 - PCK3 Main Oscillator Input Main Oscillator Output PLL Filter Programmable Clock Output Input Output Input Output ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Input Input Output Input Input Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Reset/Test NRST TST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input PIO PA0 - PA30 PB0 - PB30 Parallel IO Controller A Parallel IO Controller B I/O I/O Pulled-up input at reset Pulled-up input at reset Input Input Input Output I/O Input Low High Pull-Up resistor, Open Drain Output Pull-down resistor Input High Pull-down resistor No pull-up resistor. Pull-down resistor. No pull-up resistor No pull-up resistor.
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Table 4-1.
Signal Name
Signal Description List (Continued)
Function Type USB Device Port Active Level Comments
DDM DDP
USB Device Port Data USB Device Port Data + USART
Analog Analog
SCK0 - SCK1 TXD0 - TXD1 RXD0 - RXD1 RTS0 - RTS1 CTS0 - CTS1 DCD1 DTR1 DSR1 RI1
Serial Clock Transmit Data Receive Data Request To Send Clear To Send Data Carrier Detect Data Terminal Ready Data Set Ready Ring Indicator
I/O I/O Input Output Input Input Output Input Input Synchronous Serial Controller
TD RD TK RK TF RF
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input I/O I/O I/O I/O Timer/Counter
TCLK0 - TCLK2 TIOA0 - TIOA2 TIOB0 - TIOB2
External Clock Inputs I/O Line A I/O Line B
Input I/O I/O PWM Controller
PWM0 - PWM3
PWM Channels
Output Serial Peripheral Interface - SPIx
SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1-NPCS3
Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select 1 to 3
I/O I/O I/O I/O Output Low Low
Two-wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O
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AT91SAM7X256/128 Preliminary
Table 4-1.
Signal Name
Signal Description List (Continued)
Function Type Analog-to-Digital Converter Active Level Comments
AD0-AD3 AD4-AD7 ADTRG ADVREF
Analog Inputs Analog Inputs ADC Trigger ADC Reference
Analog Analog Input Analog Fast Flash Programming Interface
Digital pulled-up inputs at reset Analog Inputs
PGMEN0-PGMEN1 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD
Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command
Input Input I/O Output Output Input Input Input CAN Controller Low High Low Low
CANRX CANTX
CAN Input CAN Output
Input Output Ethernet MAC 10/100
EREFCK ETXCK ERXCK ETXEN ETX0 - ETX3 ETXER ERXDV ECRSDV ERX0 - ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Reference Clock Transmit Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Carrier Sense and Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force 100 Mbits/sec.
Input Input Input Output Output Output Input Input Input Input Input Input Output I/O Output High
RMII only MII only MII only
ETX0 - ETX1 only in RMII MII only MII only RMII only ERX0 - ERX1 only in RMII
MII only MII only
RMII only
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5. Package
The AT91SAM7X256/128 is available in 100-lead LQFP package.
5.1
100-lead LQFP Mechanical Overview
Figure 5-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet. Figure 5-1. 100-lead LQFP Package Pinout (Top View)
75 76
51 50
100 1 25
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5.2
AT91SAM7X256/128 Pinout
Pinout in 100-lead TQFP Package
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA18/PGMD6 PB9 PB8 PB14 PB13 PB6 GND VDDIO PB5 PB15 PB17 VDDCORE PB7 PB12 PB0 PB1 PB2 PB3 PB10 PB11 PA19/PGMD7 PA20/PGMD8 VDDIO PA21/PGMD9 PA22/PGMD10 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TDI GND PB16 PB4 PA23/PGMD11 PA24/PGMD12 NRST TST PA25/PGMD13 PA26/PGMD14 VDDIO VDDCORE PB18 PB19 PB20 PB21 PB22 GND PB23 PB24 PB25 PB26 PA27/PGMD15 PA28 PA29 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TDO JTAGSEL TMS TCK PA30 PA0/PGMEN0 PA1/PGMEN1 GND VDDIO PA3 PA2 VDDCORE PA4/PGMNCMD PA5/PGMRDY PA6/PGMNOE PA7/PGMNVALID ERASE DDM DDP VDDFLASH GND XIN/PGMCK XOUT PLLRC VDDPLL
Table 5-1.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
ADVREF GND AD4 AD5 AD6 AD7 VDDOUT VDDIN PB27/AD0 PB28/AD1 PB29/AD2 PB30/AD3 PA8/PGMM0 PA9/PGMM1 VDDCORE GND VDDIO PA10/PGMM2 PA11/PGMM3 PA12/PGMD0 PA13/PGMD1 PA14/PGMD2 PA15/PGMD3 PA16/PGMD4 PA17/PGMD5
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6. Power Considerations
6.1 Power Supplies
The AT91SAM7X256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: * VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. If the voltage regulator and the ADC are not used, VDDIN should be connected to GND. * VDDOUT pin. It is the output of the 1.8V voltage regulator. * VDDIO pin. It powers the I/O lines; voltage ranges from 3.0V to 3.6V, 3.3V nominal. * VDDFLASH pin. It powers the USB transceivers and a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal. * VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly. * VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin. No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.
6.2
Power Consumption
The AT91SAM7X256/128 has a static current of less than 60 A on VDDCORE at 25C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 A static current. The dynamic power consumption on VDDCORE is less than 90 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.
6.3
Voltage Regulator
The AT91SAM7X256/128 embeds a voltage regulator that is managed by the System Controller. In Normal Mode, the voltage regulator consumes less than 100 A static current and draws 100 mA of output current. The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 A static current and draws 1 mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor should be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 F (or 3.3 F) X7R capacitor should be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 F X7R.
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6.4
Typical Powering Schematics
The AT91SAM7X256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 6-1 shows the power schematics to be used for USB bus-powered systems. Figure 6-1. 3.3V System Single Power Supply Schematic
VDDFLASH Power Source ranges from 4.5V (USB) to 18V
DC/DC Converter
VDDIO
VDDIN 3.3V VDDOUT Voltage Regulator
VDDCORE
VDDPLL
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7. I/O Lines Considerations
7.1 JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations.
7.2
Test Pin
The TST pin is used for manufacturing test or fast programming mode of the AT91SAM7X256/128 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low. Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
7.3
Reset Pin
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset all the components of the system. The NRST pin integrates a permanent pull-up resistor to VDDIO.
7.4
ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 k to GND, so that it can be left unconnected for normal operations. This pin is debounced by the RC oscillator to improve the glitch tolerance. Minimum debouncing time is 200 ms.
7.5
PIO Controller Lines
All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset.
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7.6
I/O Lines Current Drawing
The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA.
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8. Processor and Architecture
8.1 ARM7TDMI Processor
* RISC processor based on ARMv4T Von Neumann architecture - Runs at up to 55 MHz, providing 0.9 MIPS/MHz * Two instruction sets - ARM(R) high-performance 32-bit instruction set - Thumb(R) high code density 16-bit instruction set * Three-stage pipeline architecture - Instruction Fetch (F) - Instruction Decode (D) - Execute (E)
8.2
Debug and Test Features
* Integrated embedded in-circuit emulator - Two watchpoint units - Test access port accessible through a JTAG protocol - Debug communication channel * Debug Unit - Two-pin UART - Debug communication channel interrupt handling - Chip ID Register * IEEE1149.1 JTAG Boundary-scan on all digital pins
8.3
Memory Controller
* Programmable Bus Arbiter - Handles requests from the ARM7TDMI, the Ethernet MAC and the Peripheral DMA Controller * Address decoder provides selection signals for - Three internal 1 Mbyte memory areas - One 256 Mbyte embedded peripheral area * Abort Status Registers - Source, Type and all parameters of the access leading to an abort are saved - Facilitates debug by detection of bad pointers * Misalignment Detector - Alignment checking of all data accesses - Abort generation in case of misalignment * Remap Command - Remaps the SRAM in place of the embedded non-volatile memory - Allows handling of dynamic exception vectors
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* Embedded Flash Controller - Embedded Flash interface, up to three programmable wait states - Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states - Key-protected program, erase and lock/unlock sequencer - Single command for erasing, programming and locking operations - Interrupt generation in case of forbidden operation
8.4
Peripheral DMA Controller
* Handles data transfer between peripherals and memories * Seventeen channels - Two for each USART - Two for the Debug Unit - Two for the Serial Synchronous Controller - Two for each Serial Peripheral Interface - Two for the Advanced Encryption Standard 128-bit accelerator - Two for the Triple Data Standard Encryption 128-bit acceleratorOne for the Analogto-digital Converter * Low bus arbitration overhead - One Master Clock cycle needed for a transfer from memory to peripheral - Two Master Clock cycles needed for a transfer from peripheral to memory * Next Pointer management for reducing interrupt latency requirements
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9. Memory
9.1 AT91SAM7X256
* 256 Kbytes of Flash Memory - 1024 pages of 256 bytes - Fast access time, 30 MHz single-cycle access in Worst Case conditions - Page programming time: 6 ms, including page auto-erase - Page programming without auto-erase: 3 ms - Full chip erase time: 15 ms - 10,000 write cycles, 10-year data retention capability - 16 lock bits, each protecting 16 sectors of 64 pages - Protection Mode to secure contents of the Flash * 64 Kbytes of Fast SRAM - Single-cycle access at full speed
9.2
AT91SAM7X128
* 128 Kbytes of Flash Memory - 512 pages of 256 bytes - Fast access time, 30 MHz single-cycle access in Worst Case conditions - Page programming time: 6 ms, including page auto-erase - Page programming without auto-erase: 3 ms - Full chip erase time: 15 ms - 10,000 write cycles, 10-year data retention capability - 8 lock bits, each protecting 8 sectors of 64 pages - Protection Mode to secure contents of the Flash * 32 Kbytes of Fast SRAM - Single-cycle access at full speed
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9.3
9.3.1
Memory Mapping
Internal RAM * The AT91SAM7X256 embeds a high-speed 64-Kbyte SRAM bank * The AT91SAM7X128 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.
9.3.2
Internal ROM The AT91SAM7X256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains FFPI and SAM-BA program.
9.3.3
Internal Flash * The AT91SAM7X256 features one bank of 256 Kbytes of Flash * The AT91SAM7X128 features one bank of 128 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command. A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash. This GPNVM bit can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface. Setting the GPNVM Bit 2 selects the boot from the Flash. Asserting ERASE clears the GPNVM Bit 2 and thus selects the boot from the ROM by default. Figure 9-1. Internal Memory Mapping with GPNVM Bit 2 = 0 (default)
0x0000 0000
0x000F FFFF
ROM Before Remap SRAM After Remap Internal FLASH
1 M Bytes
0x0010 0000 1 M Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
1 M Bytes 1 M Bytes 252 M Bytes
Internal ROM
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
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Figure 9-2. Internal Memory Mapping with GPNVM bit 2 = 1
0x0000 0000
0x000F FFFF
Flash Before Remap SRAM After Remap Internal FLASH
1 M Bytes
0x0010 0000 1 M Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
1 M Bytes 1 M Bytes 252 M Bytes
Internal ROM
0x003F FFFF 0x0040 0000
Undefined Areas (Abort)
0x0FFF FFFF
9.4
9.4.1
Embedded Flash
Flash Overview * The Flash of the AT91SAM7X256 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. * The Flash of the AT91SAM7X128 is organized in 512 pages of 256 bytes. It reads as 32,768 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions. When Flash is not used (read or write access), it is automatically placed into standby mode.
9.4.2
Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows: * programming of the access parameters of the Flash (number of wait states, timings, etc.) * starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. * getting the end status of the last command * getting error status * programming interrupts on the end of the last commands or on errors The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.
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9.4.3 9.4.3.1
Lock Regions AT91SAM7X256 The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region's erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 16 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.4.3.2
AT91SAM7X128 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region's erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 8 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
9.4.4
Security Bit Feature The AT91SAM7X256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command "Set Security Bit" of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 200 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.
9.4.5
Non-volatile Brownout Detector Control Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state. These two GPNVM bits can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface.
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* GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default. * The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default. 9.4.6 Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
9.5
Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 tied to low.
9.6
SAM-BA Boot Assistant
The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program insitu the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. * Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection. * Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when the GPNVM Bit 2 is set to 0.
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10. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 10-1. System Controller Block Diagram
System Controller
jtag_nreset
Boundary Scan TAP Controller
irq0-irq1 fiq periph_irq[2..19]
nirq
Advanced Interrupt Controller
int
nfiq proc_nreset PCK debug
ARM7TDMI
pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset cal gpnvm[0] en gpnvm[1] flash_wrdis ice_nreset jtag_nreset bod_rst_en dbgu_irq force_ntrst dbgu_txd
ice_nreset force_ntrst
Debug Unit
security_bit
Periodic Interval Timer Real-Time Timer Watchdog Timer
wdt_fault WDRPROC
pit_irq
flash_poe rtt_irq flash_wrdis cal wdt_irq gpnvm[0..2]
Embedded Flash
efc_irq MCK proc_nreset
BOD
Memory Controller
POR
Reset Controller
periph_nreset proc_nreset
flash_poe rstc_irq SLCK
NRST
Voltage Regulator Mode Controller
standby
Voltage Regulator
cal
RCOSC
XIN
SLCK
periph_clk[2..18] pck[0-3]
UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend
OSC
XOUT
MAINCK
Power Management Controller
PCK UDPCK MCK
USB Device Port
PLLRC
PLL
PLLCK pmc_irq int idle periph_clk[4..19] periph_nreset
periph_nreset usb_suspend
periph_nreset periph_clk[2-3] dbgu_rxd
periph_irq{2-3] irq0-irq1
Embedded Peripherals
periph_irq[4..19]
PIO Controller
fiq dbgu_txd
in PA0-PA30 PB0-PB30 out enable
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10.1 System Controller Mapping
The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 10-2 shows the mapping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space. Figure 10-2. System Controller Mapping
Address
0xFFFF F000
Peripheral
Peripheral Name
Size
AIC
0xFFFF F1FF 0xFFFF F200
Advanced Interrupt Controller
512 Bytes/128 registers
DBGU
0xFFFF F3FF 0xFFFF F400
Debug Unit
512 Bytes/128 registers
PIOA
0xFFFF F5FF 0xFFFF F600
PIO Controller A
512 Bytes/128 registers
PIOB
0xFFFF F7FF 0xFFFF F800
PIO Controller B
512 Bytes/128 registers
Reserved
0xFFFF FBFF 0xFFFF FC00
PMC
0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00
Power Management Controller Reset Controller Real-time Timer Periodic Interval Timer Watchdog Timer Voltage Regulator Mode Controller
256 Bytes/64 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 4 Bytes/1 register
RSTC Reserved RTT PIT WDT Reserved VREG Reserved
MC
0xFFFF FFFF
Memory Controller
256 Bytes/64 registers
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10.2
Reset Controller
* Based on one power-on reset cell and one brownout detector * Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset * Controls the internal resets and the NRST pin output * Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement.
10.2.1
Brownout Detector and Power-on Reset The AT91SAM7X256/X128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or powerdown sequences or if brownouts occur on the power supplies. The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device. The brownout detector monitors the VDDCORE and VDDFLASH levels during operation by comparing them to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE or VDDFLASH. When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot18-, defined as Vbot18 - hyst/2), the brownout output is immediately activated. When VDDCORE increases above the trigger level (Vbot18+, defined as Vbot18 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1s. The VDDCORE threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of 2% and is factory calibrated. When the brownout detector is enabled and VDDFLASH decreases to a value below the trigger level (Vbot33-, defined as Vbot33 - hyst/2), the brownout output is immediately activated. When VDDFLASH increases above the trigger level (Vbot33+, defined as Vbot33 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1s. The VDDFLASH threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 2.80V with an accuracy of 3.5% and is factory calibrated. The brownout detector is low-power, as it consumes less than 28 A static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1A. The deactivation is configured through the GPNVM bit 0 of the Flash.
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10.3 Clock Generator
The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: * RC Oscillator ranges between 22 KHz and 42 KHz * Main Oscillator frequency ranges between 3 and 20 MHz * Main Oscillator can be bypassed * PLL output ranges between 80 and 220 MHz It provides SLCK, MAINCK and PLLCK. Figure 10-3. Clock Generator Block Diagram
Clock Generator
Embedded RC Oscillator
Slow Clock SLCK
XIN XOUT
Main Oscillator
Main Clock MAINCK
PLLRC
PLL and Divider
PLL Clock PLLCK
Status
Control
Power Management Controller
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10.4
Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide: * the Processor Clock PCK * the Master Clock MCK * the USB Clock UDPCK * all the peripheral clocks, independently controllable * four programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. Figure 10-4. Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int
periph_clk[2..18]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64
pck[0..3]
USB Clock Controller ON/OFF PLLCK Divider /1,/2,/4
UDPCK
10.5
Advanced Interrupt Controller
* Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor * Individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) - Other sources control the peripheral interrupts or external interrupts - Programmable edge-triggered or level-sensitive internal sources - Programmable positive/negative edge-triggered or high/low level-sensitive external sources * 8-level Priority Controller - Drives the normal interrupt nIRQ of the processor - Handles priority of the interrupt sources
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- Higher priority interrupts can be served during service of lower priority interrupt * Vectoring - Optimizes interrupt service routine branch and execution - One 32-bit vector register per interrupt source - Interrupt vector register reads the corresponding current interrupt vector * Protect Mode - Easy debugging by preventing automatic operations * Fast Forcing - Permits redirecting any interrupt source on the fast interrupt * General Interrupt Mask - Provides processor synchronization on events without triggering an interrupt
10.6
Debug Unit
* Comprises: - One two-pin UART - One Interface for the Debug Communication Channel (DCC) support - One set of Chip ID Registers - One Interface providing ICE Access Prevention * Two-pin UART - USART-compatible User Interface - Programmable Baud Rate Generator - Parity, Framing and Overrun Error - Automatic Echo, Local Loopback and Remote Loopback Channel Modes * Debug Communication Channel Support - Offers visibility of COMMRX and COMMTX signals from the ARM Processor * Chip ID Registers - Identification of the device revision, sizes of the embedded memories, set of peripherals - Chip ID is 0x271B 0940 (VERSION 0) for AT91SAM7X256 - Chip ID is 0x271A 0740 (VERSION 0) for AT91SAM7X128
10.7
Period Interval Timer
* 20-bit programmable counter plus 12-bit interval counter
10.8
Watchdog Timer
* 12-bit key-protected Programmable Counter running on prescaled SLCK * Provides reset or interrupt signals to the system * Counter may be stopped while the processor is in debug state or in idle mode
10.9
Real-time Timer
* 32-bit free-running counter with alarm running on prescaled SLCK * Programmable 16-bit prescaler for SLCK accuracy compensation 25
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10.10 PIO Controllers
* Two PIO Controllers, each controlling 31 I/O lines * Fully programmable through set/clear registers * Multiplexing of two peripheral functions per I/O line * For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) - Input change interrupt - Half a clock period glitch filter - Multi-drive option enables driving in open drain - Programmable pull-up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time * Synchronous output, provides Set and Clear of several I/O lines in a single write
10.11 Voltage Regulator Controller
The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).
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11. Peripherals
11.1 Peripheral Mapping
Each peripheral is allocated 16 Kbytes of address space. Figure 11-1. User Peripheral Mapping
Peripheral Name
0xF000 0000
Size Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF
TC0, TC1, TC2
Timer/Counter 0, 1 and 2
16 Kbytes
0xFFFA 4000 AES 128
0xFFFA 7FFF
Advanced Encryption Standard 128-bit Triple Data Encryption Standard
16 Kbytes
0xFFFA 8000 TDES
0xFFFA BFFF 0xFFFA C000
16 Kbytes
Reserved
0xFFFA FFFF
0xFFFB 0000
0xFFFB 3FFF 0xFFFB 4000
UDP
USB Device Port
16 Kbytes
Reserved
0xFFFB 7FFF
0xFFFB 8000
0xFFFB BFFF 0xFFFB C000
TWI
Two-Wire Interface
16 Kbytes
Reserved 0xFFFC 0000
0xFFFB FFFF
USART0
0xFFFC 3FFF
Universal Synchronous Asynchronous Receiver Transmitter 0 Universal Synchronous Asynchronous Receiver Transmitter 1
16 Kbytes 16 Kbytes
0xFFFC 4000 USART1
0xFFFC 7FFF
0xFFFC 8000 Reserved
0xFFFC BFFF
0xFFFC C000 PWMC
0xFFFC FFFF
PWM Controller
16 Kbytes
0xFFFD 0000 CAN
0xFFFD 3FFF
CAN Controller
16 Kbytes
0xFFFD 4000
0xFFFD 7FFF
SSC
Serial Synchronous Controller
16 Kbytes
0xFFFD 8000
0xFFFD BFFF
ADC
Analog-to-Digital Converter
16 Kbytes
0xFFFD C000
0xFFFD FFFF
EMAC
Ethernet MAC
16 Kbytes 16 Kbytes
0xFFFE 0000
0xFFFE 3FFF
SPI0
Serial Peripheral Interface 0
0xFFFE 4000
0xFFFE 7FFF 0xFFFE 8000
SPI1
Serial Peripheral Interface 1
16 Kbytes
Reserved
0xFFFE FFFF
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11.2
Peripheral Multiplexing on PIO Lines
The AT91SAM7X256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller. Table 11-1 on page 29 and Table 11-2 on page 30 defines how the I/O lines of the peripherals A, B or the analog inputs are multiplexed on the PIO Controller A and PIO Controller B. The two columns "Function" and "Comments" have been inserted for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only, may be duplicated in the table. At reset, all I/O lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected.
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11.3 PIO Controller A Multiplexing
Table 11-1.
Multiplexing on PIO Controller A
PIO Controller A Application Usage Comments High-Drive High-Drive SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 High-Drive High-Drive Function Comments
I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30
Peripheral A RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 TWD TWCK SPI_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK CANRX CANTX TF TK TD RD RK RF DRXD DTXD FIQ IRQ0
Peripheral B
SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3
PCK1 IRQ1 TCLK2
SPI1_NPCS0 SPI1_SPCK SPI1_MOSI SPI1_MISO SPI1_NPCS1 SPI1_NPCS2 PCK3
SPI1_NPCS3 PCK2
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11.4
PIO Controller B Multiplexing
Table 11-2.
Multiplexing on PIO Controller B
PIO Controller A Application Usage Comments Function Comments
I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30
Peripheral A ETXCK/EREFCK ETXEN ETX0 ETX1 ECRS ERX0 ERX1 ERXER EMDC EMDIO ETX2 ETX3 ETXER ERX2 ERX3 ERXDV/ECRSDV ECOL ERXCK EF100 PWM0 PWM1 PWM2 PWM3 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 PCK1 PCK2
Peripheral B PCK0
SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2
SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 RI1 PWM0 PWM1 PWM2 PWM3 AD0 AD1 AD2 AD3
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11.5 Peripheral Identifiers
The AT91SAM7X256/128 embeds a wide range of peripherals. Table 11-3 defines the Peripheral Identifiers of the AT91SAM7X256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller.
Table 11-3.
Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20-29 30 31
Peripheral Identifiers
Peripheral Mnemonic AIC SYSIRQ PIOA PIOB SPI0 SPI1 US0 US1 SSC TWI PWMC UDP TC0 TC1 TC2 CAN EMAC ADC AES TDES Reserved AIC AIC Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1
(1) (1)
Peripheral Name Advanced Interrupt Controller
External Interrupt FIQ
Parallel I/O Controller A Parallel I/O Controller B Serial Peripheral Interface 0 Serial Peripheral Interface 1 USART 0 USART 1 Synchronous Serial Controller Two-wire Interface Pulse Width Modulation Controller USB device Port Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 CAN Controller Ethernet MAC Analog-to Digital Converter Advanced Encryption Standard 128-bit Triple Data Encryption Standard
Note:
1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller and ADC are continuously clocked.
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11.6
Ethernet MAC
* DMA Master on Receive and Transmit Channels * Compatible with IEEE Standard 802.3 * 10 and 100 Mbit/s operation * Full- and half-duplex operation * Statistics Counter Registers * MII/RMII interface to the physical layer * Interrupt generation to signal receive and transmit completion * 28-byte transmit FIFO and 28-byte receive FIFO * Automatic pad and CRC generation on transmitted frames * Automatic discard of frames received with errors * Address checking logic supports up to four specific 48-bit addresses * Support Promiscuous Mode where all valid received frames are copied to memory * Hash matching of unicast and multicast destination addresses * Physical layer management through MDIO interface * Half-duplex flow control by forcing collisions on incoming frames * Full-duplex flow control with recognition of incoming pause frames * Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames * Multiple buffers per receive and transmit frame * Jumbo frames up to 10240 bytes supported
11.7
Serial Peripheral Interface
* Supports communication with external serial devices - Four chip selects with external decoder allow communication with up to 15 peripherals - Serial memories, such as DataFlash(R) and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays per chip select, between consecutive transfers and between clock and data - Programmable delay between consecutive transfers - Selectable mode fault detection - Maximum frequency at up to Master Clock
11.8
Two-wire Interface
* Master Mode only * Compatibility with standard two-wire serial memories
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* One, two or three bytes for slave address * Sequential read/write operations
11.9
USART
* Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode - 1 or 2 stop bits in Synchronous Mode - Parity generation and error detection - Framing error detection, overrun error detection - MSB or LSB first - Optional break generation and detection - By 8 or by 16 over-sampling receiver frequency - Hardware handshaking RTS - CTS - Modem Signals Management DTR-DSR-DCD-RI on USART1 - Receiver time-out and transmitter timeguard - Multi-drop Mode with address generation and detection * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * IrDA modulation and demodulation - Communication at up to 115.2 Kbps * Test Modes - Remote Loopback, Local Loopback, Automatic Echo
11.10 Serial Synchronous Controller
* Provides serial synchronous communication links used in audio and telecom applications * Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
11.11 Timer Counter
* Three 16-bit Timer Counter Channels - Three output compare or two input capture * Wide range of functions including: - Frequency measurement - Event counting - Interval measurement - Pulse generation 33
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- Delay timing - Pulse Width Modulation - Up/down capabilities * Each channel is user-configurable and contains: - Three external clock inputs * Five internal clock inputs, as defined in Table 11-4 Table 11-4. Timer Counter Clocks Assignment
Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5
- Two multi-purpose input/output signals - Two global registers that act on all three TC channels
11.12 Pulse Width Modulation Controller
* Four channels, one 16-bit counter per channel * Common clock generator, providing thirteen different clocks - One Modulo n counter providing eleven clocks - Two independent linear dividers working on modulo n counter outputs * Independent channel programming - Independent enable/disable commands - Independent clock selection - Independent period and duty cycle, with double buffering - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform
11.13 USB Device Port
* USB V2.0 full-speed compliant,12 Mbits per second * Embedded USB V2.0 full-speed transceiver * Embedded 1352-byte dual-port RAM for endpoints * Six endpoints - Endpoint 0: 8 bytes - Endpoint 1 and 2: 64 bytes ping-pong - Endpoint 3: 64 bytes - Endpoint 4 and 5: 256 bytes ping-pong - Ping-pong Mode (two memory banks) for bulk endpoints * Suspend/resume logic
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11.14 CAN Controller
* * * Fully compliant with CAN 2.0A and 2.0B Bit rates up to 1Mbit/s Eight object oriented mailboxes each with the following properties: - CAN Specification 2.0 Part A or 2.0 Part B Programmable for each Message - Object configurable to receive (with overwrite or not) or transmit - Local tag and mask filters up to 29-bit identifier/channel - 32-bit access to data registers for each mailbox data object - Uses a 16-bit time stamp on receive and transmit message - Hardware concatenation of ID unmasked bitfields to speedup family ID processing - 16-bit internal timer for time stamping and network synchronization - Programmable reception buffer length up to 8 mailbox objects - Priority management between transmission mailboxes - Autobaud and listening mode - Low power mode and programmable wake-up on bus activity or by the application - Data, remote, error and overload frame handling
11.15 128-bit Advanced Encryption Standard
* Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) * 128-bit Cryptographic Key * 12-clock Cycles Encryption/Decryption Processing Time * Support of the Five Standard Modes of Operation specified in the NIST Special Publication 800-38A: - Electronic Codebook (ECB) - Cipher Block Chaining (CBC) - Cipher Feedback (CFB) - Output Feedback (OFB) - Counter (CTR) * 8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode * Last Output Data Mode allowing Message Authentication Code (MAC) generation * Hardware Countermeasures against Differential Power Analysis attacks * Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes: - One Channel for the Receiver, One Channel for the Transmitter - Next Buffer Support AES 128-bit Key Algorithm Hardware Accelerator
11.16 Triple Data Encryption Standard
* Single Data Encryption Standard (DES) and Triple Data Encryption * Algorithm (TDEA or TDES) supports * Compliant with FIPS Publication 46-3, Data Encryption Standard (DES) * 64-bit Cryptographic Key * Two-key or Three-key Algorithms
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* 18-clock Cycles Encryption/Decryption Processing Time for DES * 50-clock Cycles Encryption/Decryption Processing Time for TDES * Support the Four Standard Modes of Operation specified in the FIPS Publication 81, DES * Modes of Operation: - Electronic Codebook (ECB) - Cipher Block Chaining (CBC) - Cipher Feedback (CFB) - Output Feedback (OFB) * 8-, 16-, 32- and 64- Data Sizes Possible in CFB Mode * Last Output Data Mode allowing Optimized Message (Data) Authentication Code (MAC) generation * Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes: - One Channel for the Receiver, One Channel for the Transmitter - Next Buffer Support
11.17 Analog-to-Digital Converter
* 8-channel ADC * 10-bit 384 Ksamples/sec. Successive Approximation Register ADC * -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity * Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs * External voltage reference for better accuracy on low voltage inputs * Individual enable and disable of each channel * Multiple trigger sources - Hardware or software trigger - External trigger pin - Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger * Sleep Mode and conversion sequencer - Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels * Four of eight analog inputs shared with digital signals
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12. ARM7TDMI Processor Overview
12.1 Overview
The ARM7TDMI core executes both the 32-bit ARM(R) and 16-bit Thumb(R) instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages. The main features of the ARM7tDMI processor are: * ARM7TDMI Based on ARMv4T Architecture * Two Instruction Sets - ARM(R) High-performance 32-bit Instruction Set - Thumb(R) High Code Density 16-bit Instruction Set * Three-Stage Pipeline Architecture - Instruction Fetch (F) - Instruction Decode (D) - Execute (E)
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12.2
ARM7TDMI Processor
For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B)
12.2.1
Instruction Type Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
12.2.2
Data Type ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries. Unaligned data access behavior depends on which instruction is used where.
12.2.3
ARM7TDMI Operating Mode The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes: User: The normal ARM program execution state FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system Abort mode: Implements virtual memory and/or memory protection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources.
12.2.4
ARM7TDMI Registers The ARM7TDMI processor has a total of 37registers: * 31 general-purpose 32-bit registers * 6 status registers These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer. At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer.
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Table 12-1.
User and System Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC
ARM7TDMI ARM Modes and Registers Layout
Supervisor Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC
Abort Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC
Undefined Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC
Interrupt Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC
Fast Interrupt Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC
CPSR
CPSR SPSR_SVC
CPSR SPSR_ABORT
CPSR SPSR_UNDEF
CPSR SPSR_IRQ
CPSR SPSR_FIQ
Mode-specific banked registers
Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a generalpurpose register to be specified. Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor. 12.2.4.1 Modes and Exception Handling All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers. 39
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A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 12.2.4.2 Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: * four ALU flags (Negative, Zero, Carry, and Overflow) * two interrupt disable bits (one for each type of interrupt) * one bit to indicate ARM or Thumb execution * five bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception. 12.2.4.3 Exception Types
The ARM7TDMI supports five types of exception and a privileged processing mode for each type.
The types of exceptions are: * fast interrupt (FIQ) * normal interrupt (IRQ) * memory aborts (used to implement memory protection or virtual memory) * attempted execution of an undefined instruction * software interrupts (SWIs) Exceptions are generated by internal and external sources. More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state. To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways: * by using a data-processing instruction with the S-bit set, and the PC as the destination * by using the Load Multiple with Restore CPSR instruction (LDM) 12.2.5 ARM Instruction Set Overview The ARM instruction set is divided into: * Branch instructions * Data processing instructions * Status register transfer instructions * Load and Store instructions * Coprocessor instructions * Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 12-2 gives the ARM instruction mnemonic list. 40
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Table 12-2.
Mnemonic
MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC
ARM Instruction Mnemonic List
Operation
Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor
Mnemonic
CDP MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR STRH STRB STRBT STRT STM SWPB MRC STC
Operation
Coprocessor Data Processing Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor
12.2.6
Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: * Branch instructions * Data processing instructions * Load and Store instructions * Load and Store Multiple instructions * Exception-generating instruction In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the
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Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 12-3 gives the Thumb instruction mnemonic list. Table 12-3.
Mnemonic
MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH
Thumb Instruction Mnemonic List
Operation
Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack BL SWI STR STRH STRB LDRSB STMIA POP Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack
Mnemonic
MVN ADC SBC CMN NEG BIC ORR LSR ROR
Operation
Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right
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13. Debug and Test Features
13.1 Description
The AT91SAM7X Series features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.
13.2
Block Diagram
Figure 13-1. Debug and Test Block Diagram
TMS TCK TDI
Boundary TAP
ICE/JTAG TAP
JTAGSEL TDO
ICE
Reset and Test
POR TST
ARM7TDMI
PIO
DTXD DRXD
PDC
DBGU
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13.3
13.3.1
Application Examples
Debug Environment Figure 13-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 13-2. Application Debug Environment Example
Host Debugger ICE/JTAG Interface
ICE/JTAG Connector
AT91SAM7Xxx
RS232 Connector
Terminal
AT91SAM7Xxx-based Application Board
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13.3.2 Test Environment Figure 13-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the "board in test" is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 13-3. Application Test Environment Example
Test Adaptor
Tester
JTAG Interface
ICE/JTAG Connector
Chip n
Chip 2
AT91SAM7Xxx
Chip 1
AT91SAM7Xxx-based Application Board In Test
13.4
Debug and Test Pin Description
Table 13-1.
Pin Name
Debug and Test Pin List
Function Reset/Test Type Active Level
NRST TST
Microcontroller Reset Test Mode Select ICE and JTAG
Input/Output Input
Low High
TCK TDI TDO TMS JTAGSEL
Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Debug Unit
Input Input Output Input Input
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
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13.5
13.5.1
Functional Description
Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test.
13.5.2
Embedded In-circuit Emulator The ARM7TDMI embedded In-circuit Emulator is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is examined through an ICE/JTAG port. The ARM7TDMI processor contains hardware extensions for advanced debugging features: * In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system. * In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor. There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).
13.5.3
Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel. The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM7X256 Debug Unit Chip ID value is 0x271B 0940 on 32-bit width. The AT91SAM7X128 Debug Unit Chip ID value is 0x271A 0740 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section.
13.5.4
IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds
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with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 13.5.4.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associated control signals. Each AT91SAM7X input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 13-2.
Bit Number 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 PA6/TXD1 IN/OUT PA5/RXD1 IN/OUT PA4/CTS0/SPI1_NPCS3 IN/OUT PA2/SCK0/SPI1_NPCS1 IN/OUT PA3/RTS0/SPI1_NPCS2 IN/OUT PA1/TXD0 IN/OUT PA0/RXD0 IN/OUT PA30/IRQ0/PCK2 IN/OUT
AT91SAM7X JTAG Boundary Scan Register
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL CONTROL INPUT OUTPUT
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Table 13-2.
Bit Number 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130
AT91SAM7X JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells CONTROL PA7/SCK1/SPI0_NPCS1 IN/OUT INPUT OUTPUT ERASE IN INPUT INPUT PB27/TIOA2/PWM0/AD0 IN/OUT OUTPUT CONTROL INPUT PB28/TIOB2/PWM1/AD1 IN/OUT OUTPUT CONTROL INPUT PB29/PCK1/PWM2/AD2 IN/OUT OUTPUT CONTROL INPUT PB30/PCK2/PWM3/AD3 IN/OUT OUTPUT CONTROL INPUT PA8/RTS1/SPI0_NPCS2 IN/OUT OUTPUT CONTROL INPUT PA9/CTS1/SPI0_NPCS3 IN/OUT OUTPUT CONTROL INPUT PA10/TWD IN/OUT OUTPUT CONTROL INPUT PA11/TWCK IN/OUT OUTPUT CONTROL INPUT PA12/SPI0_NPCS0 IN/OUT OUTPUT CONTROL INPUT PA13/SPI0_NPCS1/PCK1 IN/OUT OUTPUT CONTROL
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Table 13-2.
Bit Number 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 PB5/ERX0 IN/OUT PB6/ERX1 IN/OUT PB13/ERX2/SPI0_NPCS1 IN/OUT PB14/ERX3/SPI0_NPCS2 IN/OUT PB8/EMDC IN/OUT PB9/EMDIO IN/OUT PA18/SPI0_SPCK IN/OUT PA17/SPI0_MOSI IN/OUT PA16/SPI0_MISO IN/OUT PA15/SPI0_NPCS3/TCLK2 IN/OUT PA14/SPI0_NPCS2/IRQ1 IN/OUT
AT91SAM7X JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 13-2.
Bit Number 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
AT91SAM7X JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PB15/ERXDV/ECRSDV IN/OUT OUTPUT CONTROL INPUT PB17/ERXCK/SPI0_NPCS3 IN/OUT OUTPUT CONTROL INPUT PB7/ERXER IN/OUT OUTPUT CONTROL INPUT PB12/ETXER/TCLK0 IN/OUT OUTPUT CONTROL INPUT PB0/ETXCK/EREFCK/PCK0 PB0/ETXCK/ERE FCK/PCK0 OUTPUT CONTROL INPUT PB1/ETXEN PB1/ETXEN OUTPUT CONTROL INPUT PB2/ETX0 PB2/ETX0 OUTPUT CONTROL INPUT PB3/ETX1 PB3/ETX1 OUTPUT CONTROL INPUT PB10/ETX2/SPI1_NPCS1 IN/OUT OUTPUT CONTROL INPUT PB11/ETX3/SPI1_NPCS2 IN/OUT OUTPUT CONTROL INPUT PA19/CANRX IN/OUT OUTPUT CONTROL
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Table 13-2.
Bit Number 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PB19/PWM0/TCLK1 IN/OUT PB18/EF100/ADTRG IN/OUT PA26/RF/SPI1_NPCS2 IN/OUT PA25/RK/SPI1_NPCS1 IN/OUT PA24/RD/SPI1_MISO IN/OUT PA23/TD/SPI1_MOSI IN/OUT PB4/ECRS IN/OUT PB16/ECOL/SPI1_NPCS3 IN/OUT PA22/TK/SPI1_SPCK IN/OUT PA21/TF/SPI1_NPCS0 IN/OUT PA20/CANTX IN/OUT
AT91SAM7X JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 13-2.
Bit Number 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
AT91SAM7X JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PB20/PWM1/PCK0 IN/OUT OUTPUT CONTROL INPUT PB21/PWM2/PCK2 IN/OUT OUTPUT CONTROL INPUT PB22/PWM3/PCK2 IN/OUT OUTPUT CONTROL INPUT PB23/TIOA0/DCD1 IN/OUT OUTPUT CONTROL INPUT PB24/TIOB0/DSR1 IN/OUT OUTPUT CONTROL INPUT PB25/TIOA1/DTR1 IN/OUT OUTPUT CONTROL INPUT PB26/TIOB1/RI1 IN/OUT OUTPUT CONTROL INPUT PA27DRXD/PCK3 IN/OUT OUTPUT CONTROL INPUT PA28/DTXD IN/OUT OUTPUT CONTROL INPUT PA29/FIQ/SPI1_NPCS3 IN/OUT OUTPUT CONTROL
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13.5.5 ID Code Register Access: Read-only
31 30 29 28 27 26 25 24
VERSION
23 22 21 20 19
PART NUMBER
18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PART NUMBER
7 6 5 4 3
MANUFACTURER IDENTITY
2 1 0
MANUFACTURER IDENTITY
1
* VERSION[31:28]: Product Version Number Set to 0x0. * PART NUMBER[27:12]: Product Part Number AT91SAM7X256: 0x5B10 AT91SAM7X128: 0x5B0F * MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. AT91SAM7X256: JTAG ID Code value is 05B1_003F AT91SAM7X128: JTAG ID Code value is 05B0_F03F
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14. Reset Controller (RSTC)
14.1 Overview
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state.
14.2
Block Diagram
Figure 14-1. Reset Controller Block Diagram
Reset Controller
bod_rst_en brown_out Brownout Manager
bod_reset
Main Supply POR
Startup Counter
Reset State Manager
rstc_irq
proc_nreset
user_reset
NRST
nrst_out
NRST Manager
exter_nreset
periph_nreset
WDRPROC wd_fault
SLCK
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14.3
Functional Description
The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: * proc_nreset: Processor reset line. It also resets the Watchdog Timer. * periph_nreset: Affects the whole set of embedded peripherals. * nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
14.3.1
NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14-2 shows the block diagram of the NRST Manager. Figure 14-2. NRST Manager
RSTC_MR RSTC_SR
URSTIEN rstc_irq
RSTC_MR
URSTS NRSTL
Other interrupt sources user_reset
URSTEN
NRST
RSTC_MR
ERSTL nrst_out External Reset Timer exter_nreset
14.3.1.1
NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.
14.3.1.2
NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the "nrst_out" signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts
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2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 s and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. 14.3.2 Brownout Manager Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal. The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read. The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled. Figure 14-3. Brownout Manager
bod_rst_en bod_reset
RSTC_MR
BODIEN
RSTC_SR
brown_out
BODSTS
Other interrupt sources
rstc_irq
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14.3.3
Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.
14.3.3.1
Power-up Reset When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the device. The startup time, as shown in Figure 14-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset. When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately.
Figure 14-4. Power-up Reset
SLCK MCK Main Supply POR output proc_nreset periph_nreset
Any Freq.
Startup Time
Processor Startup = 3 cycles
NRST (nrst_out)
EXTERNAL RESET LENGTH = 2 cycles
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14.3.3.2 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 14-5. User Reset State
SLCK MCK
Any Freq.
NRST
Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles
proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset
NRST (nrst_out)
>= EXTERNAL RESET LENGTH
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14.3.3.3
Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered. When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset.
Figure 14-6. Brownout Reset State
SLCK MCK brown_out or bod_reset
Resynch. 2 cycles Processor Startup = 3 cycles
Any Freq.
proc_nreset RSTTYP periph_nreset Any XXX 0x5 = Brownout Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH 8 cycles (ERSTL=2)
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14.3.3.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: * PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. * PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. * EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 14-7. Software Reset
SLCK MCK
Any Freq.
Write RSTC_CR
Resynch. 1 cycle Processor Startup = 3 cycles
proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1
EXTERNAL RESET LENGTH 8 cycles (ERSTL=2)
Any
XXX
0x3 = Software Reset
SRCMP in RSTC_SR
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14.3.3.5
Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: * If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. * If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-8. Watchdog Reset
SLCK MCK
Any Freq.
wd_fault
Processor Startup = 3 cycles
proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH 8 cycles (ERSTL=2)
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14.3.4 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: * Power-up Reset * Brownout Reset * Watchdog Reset * Software Reset * User Reset Particular cases are listed below: * When in User Reset: - A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. - A software reset is impossible, since the processor reset is being activated. * When in Software Reset: - A watchdog event has priority over the current state. - The NRST has no effect. * When in Watchdog Reset: - The processor reset is active and so a Software Reset cannot be programmed. - A User Reset cannot be entered. 14.3.5 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: * RSTTYP field: This field gives the type of the last reset, as explained in previous sections. * SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. * NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. * URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 14-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. * BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt.
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Figure 14-9.
Reset Controller Status and Interrupt
MCK read RSTC_SR
Peripheral Access
2 cycle resynchronization NRST NRSTL
2 cycle resynchronization
URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1)
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14.4 Reset Controller (RSTC) User Interface
Reset Controller (RSTC) Register Mapping
Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0000 0x0000_0000
Table 14-1.
Offset 0x00 0x04 0x08
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14.4.1
Reset Controller Control Register RSTC_CR Write-only
30 29 28 KEY 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 - 20 - 12 - 4 - 19 - 11 - 3 EXTRST 18 - 10 - 2 PERRST 17 - 9 - 1 - 16 - 8 - 0 PROCRST 27 26 25 24
Register Name: Access Type:
31
* PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. * PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. * EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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14.4.2 Reset Controller Status Register RSTC_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 25 - 17 SRCMP 9 RSTTYP 1 BODSTS 24 - 16 NRSTL 8
Register Name: Access Type:
31 - 23 - 15 - 7 -
2 -
0 URSTS
* URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. * BODSTS: Brownout Detection Status 0 = No brownout high-to-low transition happened since the last read of RSTC_SR. 1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR. * RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
RSTTYP 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1
Reset Type Power-up Reset Watchdog Reset Software Reset User Reset Brownout Reset
Comments VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low BrownOut reset occurred
* NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). * SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy.
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14.4.3
Reset Controller Mode Register RSTC_MR Read/Write
30 29 28 KEY 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 - 20 - 12 - 4 URSTIEN 19 - 11 18 - 10 ERSTL 3 - 2 - 1 - 0 URSTEN 17 - 9 16 BODIEN 8 27 26 25 24
Register Name: Access Type:
31
* URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. * URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. * BODIEN: Brownout Detection Interrupt Enable 0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq. * ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 s and 2 seconds. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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15. Real-time Timer (RTT)
15.1 Overview
The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value.
15.2
Block Diagram
Figure 15-1. Real-time Timer
RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm
15.3
Functional Description
The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear.
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Figure 15-2. RTT Counting
APB cycle APB cycle
MCK
RTPRES - 1 Prescaler 0
RTT
0
...
ALMV-1
ALMV
ALMV+1
ALMV+2
ALMV+3
RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface
read RTT_SR
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15.4 Real-time Timer (RTT) User Interface
Real-time Timer (RTT) Register Mapping
Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000
Table 15-1.
Offset 0x00 0x04 0x08 0x0C
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15.4.1
Real-time Timer Mode Register RTT_MR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RTPRES 7 6 5 4 RTPRES 3 2 1 0 27 - 19 - 11 26 - 18 RTTRST 10 25 - 17 RTTINCIEN 9 24 - 16 ALMIEN 8
Register Name: Access Type:
31 - 23 - 15
* RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows: RTPRES = 0: The Prescaler Period is equal to 216 RTPRES 0: The Prescaler Period is equal to RTPRES. * ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. * RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. * RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
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15.4.2 Real-time Timer Alarm Register RTT_AR Read/Write
30 29 28 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.3 Real-time Timer Value Register RTT_VR Read-only
30 29 28 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
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15.4.4
Real-time Timer Status Register RTT_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 RTTINC 24 - 16 - 8 - 0 ALMS
Register Name: Access Type:
31 - 23 - 15 - 7 -
* ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. * RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
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16. Periodic Interval Timer (PIT)
16.1 Overview
The Periodic Interval Timer (PIT) provides the operating system's scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time.
16.2
Block Diagram
Figure 16-1. Periodic Interval Timer
PIT_MR
PIV
=?
PIT_MR
PITIEN
set
0
PIT_SR
PITS
reset
pit_irq
0
0
1
0
1
12-bit Adder
read PIT_PIVR
MCK
20-bit Counter
Prescaler
MCK/16
CPIV
PIT_PIVR
PICNT
CPIV
PIT_PIIR
PICNT
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16.3
Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 16-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state.
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Figure 16-2. Enabling/Disabling PIT with PITEN
APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle
CPIV PICNT PITS (PIT_SR) APB Interface
0
1 0
PIV - 1
PIV 1
0 0
1
read PIT_PIVR
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16.4
Periodic Interval Timer (PIT) User Interface
Periodic Interval Timer (PIT) Register Mapping
Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000
Table 16-1.
Offset 0x00 0x04 0x08 0x0C
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16.4.1 Periodic Interval Timer Mode Register PIT_MR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 PIV 7 6 5 4 PIV 3 2 1 0 27 - 19 26 - 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16
Register Name: Access Type:
31 - 23 - 15
* PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). * PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. * PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 16.4.2 Periodic Interval Timer Status Register PIT_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 PITS
Register Name: Access Type:
31 - 23 - 15 - 7 -
* PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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16.4.3
Periodic Interval Timer Value Register PIT_PIVR Read-only
30 29 28 PICNT 23 22 PICNT 15 14 13 12 CPIV 7 6 5 4 CPIV 3 2 1 0 11 10 21 20 19 18 CPIV 9 8 17 16 27 26 25 24
Register Name: Access Type:
31
Reading this register clears PITS in PIT_SR. * CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
16.4.4
Periodic Interval Timer Image Register PIT_PIIR Read-only
30 29 28 PICNT 23 22 PICNT 15 14 13 12 CPIV 7 6 5 4 CPIV 3 2 1 0 11 10 21 20 19 18 CPIV 9 8 17 16 27 26 25 24
Register Name: Access Type:
31
* CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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17. Watchdog Timer (WDT)
17.1 Overview
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.
17.2
Block Diagram
Figure 17-1. Watchdog Timer Block Diagram
write WDT_MR WDT_MR WDT_CR
WV
reload 1 0
WDRSTT
12-bit Down Counter
WDT_MR reload
WDD
Current Value
1/128
SLCK
<= WDD
WDT_MR
WDRSTEN =0
wdt_fault (to Reset Controller) set
WDUNF
set reset
wdt_int
WDERR read WDT_SR or reset
reset
WDFIEN
WDT_MR
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17.3
Functional Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz). After a Processor Reset, the value of WV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the "wdt_fault" signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur in a window defined by 0 and WDD in the WDT_MR: 0 WDT WDD; writing WDRSTT restarts the Watchdog Timer. Any attempt to restart the Watchdog Timer in the range [WDV; WDD] results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the "wdt_fault" signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal "wdt_fault" to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the "wdt_fault" signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
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Figure 17-2. Watchdog Behavior
Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 WDT_CR = WDRSTT if WDRSTEN is 0
Watchdog Fault
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17.4
Watchdog Timer (WDT) User Interface
Watchdog Timer (WDT) Register Mapping
Register Control Register Mode Register Status Register Name WDT_CR WDT_MR WDT_SR Access Write-only Read/Write Once Read-only Reset Value 0x3FFF_2FFF 0x0000_0000
Table 17-1.
Offset 0x00 0x04 0x08
17.4.1
Watchdog Timer Control Register WDT_CR Write-only
30 29 28 KEY 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 - 20 - 12 - 4 - 19 - 11 - 3 - 18 - 10 - 2 - 17 - 9 - 1 - 16 - 8 - 0 WDRSTT 27 26 25 24
Register Name: Access Type:
31
* WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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17.4.2 Watchdog Timer Mode Register WDT_MR Read/Write Once
30 - 22 29 WDIDLEHLT 21 28 WDDBGHLT 20 WDD 15 WDDIS 7 14 WDRPROC 6 13 WDRSTEN 5 12 WDFIEN 4 WDV 3 2 11 10 WDV 1 0 9 8 27 26 WDD 19 18 17 16 25 24
Register Name: Access Type:
31 - 23
* WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. * WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt. * WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset. * WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset. * WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error. * WDDBGHLT: Watchdog Debug Halt 0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. * WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. * WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.
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17.4.3
Watchdog Timer Status Register WDT_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 WDERR 24 - 16 - 8 - 0 WDUNF
Register Name: Access Type:
31 - 23 - 15 - 7 -
* WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR. * WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR.
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18. Voltage Regulator Mode Controller (VREG)
18.1 Overview
The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal Mode.
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18.2
Voltage Regulator Power Controller (VREG) User Interface
Voltage Regulator Power Controller Register Mapping
Register Voltage Regulator Mode Register Name VREG_MR Access Read/Write Reset Value 0x0
Table 18-1.
Offset 0x60
18.2.1
Voltage Regulator Mode Register VREG_MR Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 PSTDBY
Register Name: Access Type:
31 - 23 - 15 - 7 -
* PSTDBY: Periodic Interval Value 0 = Voltage regulator in normal mode. 1 = Voltage regulator in standby mode (low-power mode).
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19. Memory Controller (MC)
19.1 Overview
The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a bus arbiter, an address decoder, an abort status, a misalignment detector and an Embedded Flash Controller.
19.2
Block Diagram
Figure 19-1. Memory Controller Block Diagram
Memory Controller ASB ARM7TDMI Processor Embedded Flash Controller Abort Status Internal RAM Internal Flash
Abort
EMAC DMA
Bus Arbiter
Misalignment Detector
Address Decoder
User Interface
Peripheral DMA Controller Peripheral 0 Peripheral 1
APB Bridge
APB
From Master to Slave
Peripheral N
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19.3
Functional Description
The Memory Controller handles the internal ASB bus and arbitrates the accesses of up to three masters. It is made up of: * A bus arbiter * An address decoder * An abort status * A misalignment detector * An Embedded Flash Controller The MC handles only little-endian mode accesses. The masters work in little-endian mode only.
19.3.1
Bus Arbiter The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the three masters. The EMAC has the highest priority; the Peripheral DMA Controller has the medium priority; the ARM processor has the lowest one.
19.3.2
Address Decoder The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address bus and defines three separate areas: * One 256-Mbyte address space for the internal memories * One 256-Mbyte address space reserved for the embedded peripherals * An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed Figure 19-2 shows the assignment of the 256-Mbyte memory areas. Figure 19-2. Memory Areas
256M Bytes 0x0000 0000
0x0FFF FFFF 0x1000 0000
Internal Memories
14 x 256MBytes 3,584 Mbytes
Undefined (Abort)
0xEFFF FFFF
256M Bytes
0xF000 0000
0xFFFF FFFF
Peripherals
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19.3.2.1 Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this address space, n equaling 1M bytes divided by the size of the memory. When the address of the access is undefined within the internal memory area, the Address Decoder returns an Abort to the master. Figure 19-3. Internal Memory Mapping
0x0000 0000 Internal Memory Area 0
0x000F FFFF
1M Bytes
0x0010 0000
0x001F FFFF
Internal Memory Area 1 Internal Flash Internal Memory Area 2 Internal SRAM
1M Bytes
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
1M Bytes
Undefined Areas (Abort)
253M bytes
0x0FFF FFFF
19.3.2.2
Internal Memory Area 0 The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in particular, the Reset Vector at address 0x0. Before execution of the remap command, the on-chip Flash is mapped into Internal Memory Area 0, so that the ARM7TDMI reaches an executable instruction contained in Flash. After the remap command, the internal SRAM at address 0x0020 0000 is mapped into Internal Memory Area 0. The memory mapped into Internal Memory Area 0 is accessible in both its original location and at address 0x0.
19.3.3
Remap Command After execution, the Remap Command causes the Internal SRAM to be accessed through the Internal Memory Area 0. As the ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, and Fast Interrupt) are mapped from address 0x0 to address 0x20, the Remap Command allows the user to redefine dynamically these vectors under software control. The Remap Command is accessible through the Memory Controller User Interface by writing the MC_RCR (Remap Control Register) RCB field to one. The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset.
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19.3.4
Abort Status There are two reasons for an abort to occur: * access to an undefined address * an access to a misaligned address. When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. However, only the ARM7TDMI can take an abort signal into account, and only under the condition that it was generating an access. The Peripheral DMA Controller and the EMAC do not handle the abort input signal. Note that the connections are not represented in Figure 19-1. To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status register set. The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and include: * the size of the request (field ABTSZ) * the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP) * whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned address (bit MISADD) * the source of the access leading to the last abort (bits MST_EMAC, MST_PDC and MST_ARM) * whether or not an abort occurred for each master since the last read of the register (bits SVMST_EMAC, SVMST_PDC and SVMST_ARM) unless this information is loaded in MST bits In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as searching for which address generated the abort would require disassembling the instructions and full knowledge of the processor context. In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM processor. The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is probable that several aborts have occurred during this time. Thus, in this case, it is preferable to use the content of the Abort Link register of the ARM processor.
19.3.5
Embedded Flash Controller The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the flash block with the 32-bit internal bus. It allows an increase of performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages with the programming, erasing, locking and unlocking sequences thanks to a full set of commands.
19.3.6
Misalignment Detector The Memory Controller features a Misalignment Detector that checks the consistency of the accesses. For each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the accesses of the ARM processor when it is fetching instructions are not checked. The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particularly difficult to detect in the debug phase.
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As the requested address is saved in the Abort Status Register and the address of the instruction generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified.
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19.4
Memory Controller (MC) User Interface
Base Address: 0xFFFFFF00 Table 19-1.
Offset 0x00 0x04 0x08 0x10-0x5C 0x60
Memory Controller (MC) Register Mapping
Register MC Remap Control Register MC Abort Status Register MC Abort Address Status Register Reserved EFC Configuration Registers See Section 20. "Embedded Flash Controller (EFC)", on page 99 Name MC_RCR MC_ASR MC_AASR Access Write-only Read-only Read-only 0x0 0x0 Reset State
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19.4.1 MC Remap Control Register MC_RCR Write-only 0x0
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RCB - 23 - 15 - 7 -
Register Name: Access Type: Offset:
31
* RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices.
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19.4.2
MC Abort Status Register MC_ASR Read-only 0x0 0x04
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 3 - 27 - 19 - 11 ABTTYP 2 - 1 MISADD 26 SVMST_ARM 18 MST_ARM 10 25 SVMST_PDC 17 MST_PDC 9 ABTSZ 0 UNDADD 24 SVMST_EMAC 16 MST_EMAC 8 - 23 - 15 - 7 -
Register Name: Access Type: Reset Value: Offset:
31
* UNDADD: Undefined Address Abort Status 0: The last abort was not due to the access of an undefined address in the address space. 1: The last abort was due to the access of an undefined address in the address space. * MISADD: Misaligned Address Abort Status 0: The last aborted access was not due to an address misalignment. 1: The last aborted access was due to an address misalignment. * ABTSZ: Abort Size Status
ABTSZ 0 0 1 1 0 1 0 1 Abort Size Byte Half-word Word Reserved
* ABTTYP: Abort Type Status
ABTTYP 0 0 1 1 0 1 0 1 Abort Type Data Read Data Write Code Fetch Reserved
* MST_EMAC: EMAC Abort Source 0: The last aborted access was not due to the EMAC. 1: The last aborted access was due to the EMAC.
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* MST_PDC: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. * MST_ARM: ARM Abort Source 0: The last aborted access was not due to the ARM. 1: The last aborted access was due to the ARM. * SVMST_EMAC: Saved EMAC Abort Source 0: No abort due to the EMAC occurred since the last read of MC_ASR or it is notified in the bit MST_EMAC. 1: At least one abort due to the EMAC occurred since the last read of MC_ASR. * SVMST_PDC: Saved PDC Abort Source 0: No abort due to the PDC occurred since the last read of MC_ASR or it is notified in the bit MST_PDC. 1: At least one abort due to the PDC occurred since the last read of MC_ASR. * SVMST_ARM: Saved ARM Abort Source 0: No abort due to the ARM occurred since the last read of MC_ASR or it is notified in the bit MST_ARM. 1: At least one abort due to the ARM occurred since the last read of MC_ASR.
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19.4.3
MC Abort Address Status Register MC_AASR Read-only 0x0 0x08
30 29 28 ABTADD 23 22 21 20 ABTADD 15 14 13 12 ABTADD 7 6 5 4 ABTADD 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type: Reset Value: Offset:
31
* ABTADD: Abort Address This field contains the address of the last aborted access.
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20. Embedded Flash Controller (EFC)
20.0.1 Overview The Embedded Flash Controller (EFC) is a part of the Memory Controller and ensures the interface of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands.
20.1
20.1.1
Functional Description
Embedded Flash Organization The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several interfaces: * One memory plane organized in several pages of the same size * Two 32-bit read buffers used for code read optimization (see "Read Operations" on page 100). * One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 MByte address space, so that each word can be written to its final address (see "Write Operations" on page 102). * Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. * Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to the product definition section to get the GP NVM assignment. The Embedded Flash size, the page size and the lock region organization are described in the product definition section.
Table 20-1.
Product Specific Lock and General-purpose NVM Bits
AT91SAM7X128 3 8 Denomination Number of General-purpose NVM bits Number of Lock Bits
AT91SAM7X256 3 16
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Figure 20-1. Embedded Flash Memory Mapping
Page 0
Flash Memory
Start Address Lock Region 0 Lock Region 1
Lock Bit 0 Lock Bit 1
Page (m-1)
Lock Region (n-1)
32-bit wide
Lock Bit n-1
Page ( (n-1)*m )
Page (n*m-1)
20.1.2
Read Operations An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start access at following address during the second read, thus increasing performance when the processor is running in Thumb mode (16-bit instruction set). See Figure 20-2, Figure 20-3 and Figure 20-4. This optimization concerns only Code Fetch and not Data. The read operations can be performed with or without wait state. Up to 3 wait states can be programmed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see "MC Flash Mode Register" on page 110). Defining FWS to be 0 enables the single-cycle access of the embedded Flash. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it.
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Figure 20-2. Code Read Optimization in Thumb Mode for FWS = 0
Master Clock
ARM Request (16-bit) Code Fetch @Byte 0 Flash Access @Byte 2 @Byte 4 @Byte 6 @Byte 8 @Byte 10 @Byte 12 @Byte 14 @Byte 16
Bytes 0-3
Bytes 4-7
Bytes 8-11
Bytes 12-15
Bytes 16-19
Buffer (32 bits)
Bytes 0-3
Bytes 4-7
Bytes 8-11
Bytes 12-15
Data To ARM
Bytes 0-1
Bytes 2-3
Bytes 4-5
Bytes 6-7
Bytes 8-9
Bytes 10-11
Bytes 12-13
Bytes 14-15
Note:
When FWS is equal to 0, all accesses are performed in a single-cycle access.
Figure 20-3. Code Read Optimization in Thumb Mode for FWS = 1
1 Wait State Cycle 1 Wait State Cycle 1 Wait State Cycle 1 Wait State Cycle
Master Clock
ARM Request (16-bit) Code Fetch @Byte 0 Flash Access @Byte 2 @Byte 4 @Byte 6 @Byte 8 @Byte 10 @Byte 12 @Byte 14
Bytes 0-3
Bytes 4-7
Bytes 8-11
Bytes 12-15
Buffer (32 bits)
Bytes 0-3
Bytes 4-7
Bytes 8-11
Data To ARM
Bytes 0-1
Bytes 2-3
Bytes 4-5
Bytes 6-7
Bytes 8-9
Bytes 10-11
Bytes 12-13
Note:
When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the first one).
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Figure 20-4. Code Read Optimization in Thumb Mode for FWS = 3
3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles
Master Clock
ARM Request (16-bit) Code Fetch @Byte 0 @2 @4 @6 @8 @10 @12
Flash Access
Bytes 0-3
Bytes 4-7
Bytes 8-11
Bytes 12-15
Buffer (32 bits)
Bytes 0-3
Bytes 4-7
Bytes 8-11
Data To ARM
0-1
2-3
4-5
6-7
8-9 10-11
12-13
Note:
When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the third access FWS cycles, the fourth access one cycle, etc.
20.1.3
Write Operations The internal memory area reserved for the embedded Flash can also be written through a writeonly latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap around within the internal memory area address space and appear to be repeated 1024 times within it. Write operations can be prevented by programming the Memory Protection Unit of the product. Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. Write operations are performed in the number of wait states equal to the number of wait states for read operations + 1, except for FWS = 3 (see "MC Flash Mode Register" on page 110).
20.1.4
Flash Commands The EFC offers a command set to manage programming the memory flash, locking and unlocking lock sectors, consecutive programming and locking, and full Flash erasing. Table 20-2.
Command Write page Set Lock Bit Write Page and Lock Clear Lock Bit Erase all Set General-purpose NVM Bit Clear General-purpose NVM Bit Set Security Bit
Set of Commands
Value 0x01 0x02 0x03 0x04 0x08 0x0B 0x0D 0x0F Mnemonic WP SLB WPL CLB EA SGPB CGPB SSB
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To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command number. As soon as the MC_FCR register is written, the FRDY flag is automatically cleared. Once the current command is achieved, then the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. All the commands are protected by the same keyword, which has to be written in the eight highest bits of the MC_FCR register. Writing MC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the memory plane; however, the PROGE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register. When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the LOCKE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register.
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Figure 20-5. Command State Chart
Read Status: MC_FSR
No Check if FRDY flag set
Yes
Write FCMD and PAGENB in MC_FCR
Read Status: MC_FSR
No Check if FRDY flag set
Yes
Check if LOCKE flag set
Yes
Locking region violation
No
Check if PROGE flag set
Yes
Bad keyword violation and/or Invalid command
No Command Successful
In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle Number (FMCN) in the Flash Mode Register MC_FMR must be correctly programmed (see "MC Flash Mode Register" on page 110).
20.1.4.1
Flash Programming Several commands can be used to program the Flash. The Flash technology requires that an erase must be done before programming. The entire memory plane can be erased at the same time, or a page can be automatically erased by clearing the NEBP bit in the MC_FMR register before writing the command in the MC_FCR register.
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By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if it has been erased before (see Figure 20-6). Figure 20-6. Example of Partial Page Programming:
32 bits wide 32 bits wide 32 bits wide
FF
FF FF FF
16 words
...
FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF CA CA CA FF FF FF FF FF FF
FF FF FF FE FE FE FF FF FF FF FF FF
...
FF FF FF
FF FF FF FE FE FE FF FF FF FF FF FF
FF FF FF CA CA CA DE DE DE FF FF FF
FF FF FF FE
FF FF FF
FF ... FF FF CA ... CA CA ... DE DE DE ... FF FF FF
FF FF FF FE FE FE CA CA CA FF FF FF
16 words
FF FF FF
FF FF ... FF FF FF FF FF FF ... FF FF FF FF FF FF ... FF FF FF FF
...
CA CA CA
FE FE CA CA CA FF FF FF
...
FF FF FF
16 words
FF FF FF
...
FF FF FF
16 words
FF FF
Step 1. Erase All Flash Page 7 erased
Step 2. Programming of the second part of Page 7 (NEBP = 1)
Step 3. Programming of the third part of Page 7 (NEBP = 1)
After programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using WPL. Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size. The latch buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it.
Note: Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Data are written to the latch buffer before the programming command is written to the Flash Command Register MC_FCR. The sequence is as follows: * Write the full page, at any page address, within the internal memory area address space using only 32-bit access. * Programming starts as soon as the page number and the programming command are written to the Flash Command Register. The FRDY bit in the Flash Programming Status Register (MC_FSR) is automatically cleared. * When programming is completed, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt was enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Two errors can be detected in the MC_FSR register after a programming sequence: * Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register. * Lock Error: The page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region.
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20.1.4.2
Erase All Command The entire memory can be erased if the Erase All Command (EA) in the Flash Command Register MC_FCR is written. Erase All operation is allowed only if there are no lock bits set. Thus, if at least one lock region is locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written at 1 in MC_FMR, the interrupt line rises. When programming is complete, the bit FRDY bit in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Two errors can be detected in the MC_FSR register after a programming sequence: * Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register. * Lock Error: At least one lock region to be erased is protected. The erase command has been refused and no page has been erased. A Clear Lock Bit command must be executed previously to unlock the corresponding lock regions.
20.1.4.3
Lock Bit Protection Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages. After production, the device may have some embedded Flash lock regions locked. These locked regions are reserved for a default application. Refer to the product definition section for the default embedded Flash mapping. Locked sectors can be unlocked to be erased and then programmed with another application or other data. The lock sequence is: * The Flash Command register must be written with the following value: (0x5A << 24) | (lockPageNumber << 8 & PAGEN) | SLB lockPageNumber is a page of the corresponding lock region. * When locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. A programming error, where a bad keyword and/or an invalid command have been written in the MC_FCR register, may be detected in the MC_FSR register after a programming sequence. It is possible to clear lock bits that were set previously. Then the locked region can be erased or programmed. The unlock sequence is: * The Flash Command register must be written with the following value: (0x5A << 24) | (lockPageNumber << 8 & PAGEN) | CLB lockPageNumber is a page of the corresponding lock region. * When the unlock completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. A programming error, where a bad keyword and/or an invalid command have been written in the MC_FCR register, may be detected in the MC_FSR register after a programming sequence.
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The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR reads 0. The Lock command programs the lock bit to 0; the corresponding bit LOCKSx in MC_FSR reads 1.
Note: Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed.
20.1.4.4
General-purpose NVM Bits General-purpose NVM bits do not interfere with the embedded Flash memory plane. These general-purpose bits are dedicated to protect other parts of the product. They can be set (activated) or cleared individually. Refer to the product definition section for the general-purpose NVM bit action. The activation sequence is: * Start the Set General Purpose Bit command (SGPB) by writing the Flash Command Register with the SEL command and the number of the general-purpose bit to be set in the PAGEN field. * When the bit is set, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Two errors can be detected in the MC_FSR register after a programming sequence: * Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register * If the general-purpose bit number is greater than the total number of general-purpose bits, then the command has no effect. It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is: * Start the Clear General-purpose Bit command (CGPB) by writing the Flash Command Register with CGPB and the number of the general-purpose bit to be cleared in the PAGEN field. * When the clear completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Two errors can be detected in the MC_FSR register after a programming sequence: * Programming Error: a bad keyword and/or an invalid command have been written in the MC_FCR register * If the number of the general-purpose bit set in the PAGEN field is greater than the total number of general-purpose bits, then the command has no effect. The Clear General-purpose Bit command programs the general-purpose NVM bit to 1; the corresponding bit GPNVM0 to GPNVMx in MC_FSR reads 0. The Set General-purpose Bit command programs the general-purpose NVM bit to 0; the corresponding bit GPNVMx in MC_FSR reads 1.
Note: Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit command is performed.
20.1.4.5
Security Bit The goal of the security bit is to prevent external access to the internal bus system. JTAG, Fast Flash Programming and Flash Serial Test Interface features are disabled. Once set, this bit can be reset only by an external hardware ERASE request to the chip. Refer to the product definition
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section for the pin name that controls the ERASE. In this case, the full memory plane is erased and all lock and general-purpose NVM bits are cleared. The security bit in the MC_FSR is cleared only after these operations. The activation sequence is: * Start the Set Security Bit command (SSB) by writing the Flash Command Register. * When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the security bit is active, the SECURITY bit in the MC_FSR is set.
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20.2 Embedded Flash Controller (EFC) User Interface
Embedded Flash Controller (EFC) Register Mapping
Register MC Flash Mode Register MC Flash Command Register MC Flash Status Register Reserved Name MC_FMR MC_FCR MC_FSR - Access Read/Write Write-only Read-only - Reset State 0x0 - - -
The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. Table 20-3.
Offset 0x60 0x64 0x68 0x6C
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20.2.1
MC Flash Mode Register MC_FMR Read/Write 0x60
30 - 22 29 - 21 28 - 20 FMCN 15 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 PROGE 10 - 2 LOCKE 9 FWS 1 - 0 FRDY 8 27 - 19 26 - 18 25 - 17 24 - 16
Register Name: Access Type: Offset:
31 - 23
7 NEBP
* FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates an interrupt. * LOCKE: Lock Error Interrupt Enable 0: Lock Error does not generate an interrupt. 1: Lock Error generates an interrupt. * PROGE: Programming Error Interrupt Enable 0: Programming Error does not generate an interrupt. 1: Programming Error generates an interrupt. * NEBP: No Erase Before Programming 0: A page erase is performed before programming. 1: No erase is performed before programming. * FWS: Flash Wait State This field defines the number of wait states for read and write operations:
FWS 0 1 2 3 Read Operations 1 cycle 2 cycles 3 cycles 4 cycles Write Operations 2 cycles 3 cycles 4 cycles 4 cycles
* FMCN: Flash Microsecond Cycle Number Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond. When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds. Warning: In order to guarantee valid operations on the flash memory, the field Flash Microsecond Cycle Number (FMCN) must be correctly programmed. 110
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20.2.2 MC Flash Command Register MC_FCR Write-only 0x64
30 29 28 KEY 23 - 15 22 - 14 21 - 13 20 - 12 PAGEN 7 - 6 - 5 - 4 - 3 2 FCMD 1 0 19 - 11 18 - 10 17 PAGEN 9 8 16 27 26 25 24
Register Name: Access Type: Offset:
31
* FCMD: Flash Command This field defines the Flash commands:
FCMD 0000 0001 0010 Operations No command. Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR. Write Page Command (WP): Starts the programming of the page specified in the PAGEN field. Set Lock Bit Command (SLB): Starts a set lock bit sequence of the lock region specified in the PAGEN field. Write Page and Lock Command (WPL): The lock sequence of the lock region associated with the page specified in the field PAGEN occurs automatically after completion of the programming sequence. Clear Lock Bit Command (CLB): Starts a clear lock bit sequence of the lock region specified in the PAGEN field. Erase All Command (EA): Starts the erase of the entire Flash. If at least one page is locked, the command is cancelled. Set General-purpose NVM Bit (SGPB): Activates the general-purpose NVM bit corresponding to the number specified in the PAGEN field. Clear General Purpose NVM Bit (CGPB): Deactivates the general-purpose NVM bit corresponding to the number specified in the PAGEN field. Set Security Bit Command (SSB): Sets security bit. Reserved. Raises the Programming Error Status flag in the Flash Status Register MC_FSR.
0011
0100
1000
1011
1101
1111 Others
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* PAGEN: Page Number
Command Write Page Command Write Page and Lock Command Erase All Command Set/Clear Lock Bit Command Set/Clear General Purpose NVM Bit Command Set Security Bit Command Note: PAGEN Description PAGEN defines the page number to be written. PAGEN defines the page number to be written and its associated lock region. This field is meaningless PAGEN defines one page number of the lock region to be locked or unlocked. PAGEN defines the general-purpose bit number. This field is meaningless
Depending on the command, all the possible unused bits of PAGEN are meaningless.
* KEY: Write Protection Key This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.
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20.2.3 MC Flash Status Register MC_FSR Read-only 0x68
30 LOCKS14 22 LOCKS6 14 - 6 - 29 LOCKS13 21 LOCKS5 13 - 5 - 28 LOCKS12 20 LOCKS4 12 - 4 SECURITY 27 LOCKS11 19 LOCKS3 11 - 3 PROGE 26 LOCKS10 18 LOCKS2 10 GPNVM2 2 LOCKE 25 LOCKS9 17 LOCKS1 9 GPNVM1 1 - 24 LOCKS8 16 LOCKS0 8 GPNVM0 0 FRDY
Register Name: Access Type: Offset:
31 LOCKS15 23 LOCKS7 15 - 7 -
* FRDY: Flash Ready Status 0: The EFC is busy and the application must wait before running a new command. 1: The EFC is ready to run a new command. * LOCKE: Lock Error Status 0: No programming of at least one locked lock region has happened since the last read of MC_FSR. 1: Programming of at least one locked lock region has happened since the last read of MC_FSR. * PROGE: Programming Error Status 0: No invalid commands and no bad keywords were written in the Flash Command Register MC_FCR. 1: An invalid command and/or a bad keyword was/were written in the Flash Command Register MC_FCR. * SECURITY: Security Bit Status 0: The security bit is inactive. 1: The security bit is active. * GPNVMx: General-purpose NVM Bit Status 0: The corresponding general-purpose NVM bit is inactive. 1: The corresponding general-purpose NVM bit is active. * LOCKSx: Lock Region x Lock Status 0: The corresponding lock region is not locked. 1: The corresponding lock region is locked MC_FSR, LOCKSx Product Specific Map
AT91SAM7X256 16 LOCKS0 LOCKS1 LOCKS2 LOCKS3 LOCKS4 LOCKS5 AT91SAM7X128 8 LOCKS0 LOCKS1 LOCKS2 LOCKS3 LOCKS4 LOCKS5 Denomination Number of Lock Bits Lock Region 0 Lock Status Lock Region 1 Lock Status Lock Region 2 Lock Status Lock Region 3 Lock Status Lock Region 4 Lock Status Lock Region 5 Lock Status
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MC_FSR, LOCKSx Product Specific Map (Continued)
AT91SAM7X256 LOCKS6 LOCKS7 LOCKS8 LOCKS9 LOCKS10 LOCKS11 LOCKS12 LOCKS13 LOCKS14 LOCKS15 AT91SAM7X128 LOCKS6 LOCKS7 - - - - - - - - Denomination Lock Region 6 Lock Status Lock Region 7 Lock Status Lock Region 8 Lock Status Lock Region 9 Lock Status Lock Region 10 Lock Status Lock Region 11 Lock Status Lock Region 12 Lock Status Lock Region 13 Lock Status Lock Region 14 Lock Status Lock Region 15 Lock Status
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21. Fast Flash Programming Interface (FFPI)
21.1 Overview
The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. The serial interface uses the standard IEEE 1149.1 JTAG protocol. It offers an optimized access to all the embedded Flash functionalities. Although the Fast Flash Programming Mode is a dedicated mode for high volume programming, this mode not designed for in-situ programming.
21.2
21.2.1
Parallel Fast Flash Programming
Device Configuration In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. Figure 21-1. Parallel Programming Interface
VDDIO VDDIO VDDIO GND NCMD RDY NOE NVALID MODE[3:0] DATA[15:0] 0 - 50MHz TST PGMEN0 PGMEN1 PGMEN2 PGMNCMD PGMRDY PGMNOE PGMNVALID PGMM[3:0] PGMD[15:0] XIN
VDDCORE VDDIO VDDPLL VDDFLASH GND
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Table 21-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDFLASH VDDIO VDDCORE VDDPLL GND
Flash Power Supply I/O Lines Power Supply Core Power Supply PLL Power Supply Ground Clocks Main Clock Input. This input can be tied to GND. In this case, the device is clocked by the internal RC oscillator. Test
Power Power Power Power Ground
XIN
Input
32KHz to 50MHz
TST PGMEN0 PGMEN1 PGMEN2
Test Mode Select Test Mode Select Test Mode Select Test Mode Select PIO
Input Input Input Input
High High High Low
Must be connected to VDDIO Must be connected to VDDIO Must be connected to VDDIO Must be connected to GND
PGMNCMD PGMRDY PGMNOE PGMNVALID PGMM[3:0] PGMD[15:0]
Valid command available 0: Device is busy 1: Device is ready for a new command Output Enable (active high) 0: DATA[15:0] is in input mode 1: DATA[15:0] is in output mode Specifies DATA type (See Table 21-2) Bi-directional data bus
Input Output Input Output Input Input/Output
Low High Low Low
Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset
21.2.2
Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 21-2.
MODE[3:0] 0000 0001 0010 0011 0100 0101 Default
Mode Coding
Symbol CMDE ADDR0 ADDR1 ADDR2 ADDR2 DATA IDLE Address Register MSBs Data Register No register Data Command Register Address Register LSBs
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When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. Table 21-3.
DATA[15:0] 0x0011 0x0012 0x0022 0x0032 0x0042 0x0013 0x0014 0x0024 0x0015 0x0034 0x0044 0x0025 0x0054 0x0035 0x002F 0x001F 0x001E
Command Bit Coding
Symbol READ WP WPL EWP EWPL EA SLB CLB GLB SFB CFB GFB SSE GSE RRAM WRAM GVE Command Executed Read Flash Write Page Flash Write Page and Lock Flash Erase Page and Write Page Erase Page and Write Page then Lock Erase All Set Lock Bit Clear Lock Bit Get Lock Bit Set General Purpose NVM bit Clear General Purpose NVM bit Get General Purpose NVM bit Set Security Bit Get Security Bit Read Memory Write Memory Get Version
21.2.3
Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: * Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL. * Apply XIN clock within TPOR_RESET if an external clock is available. * Wait for TPOR_RESET * Start a read or write handshaking.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer handshake.
21.2.4
Programmer Handshaking An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once NCMD signal is high and RDY is high.
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21.2.4.1
Write Handshaking For details on the write handshaking sequence, refer to Figure 21-2and Table 21-4. Figure 21-2. Parallel Programming Timing, Write Sequence
NCMD RDY
2 3
4
5
NOE NVALID
DATA[15:0] 1 MODE[3:0]
Table 21-4.
Step 1 2 3 4 5 6
Write Handshake
Programmer Action Sets MODE and DATA signals Clears NCMD signal Waits for RDY low Releases MODE and DATA signals Sets NCMD signal Waits for RDY high Device Action Waits for NCMD low Latches MODE and DATA Clears RDY signal Executes command and polls NCMD high Executes command and polls NCMD high Sets RDY Data I/O Input Input Input Input Input Input
21.2.4.2
Read Handshaking For details on the read handshaking sequence, refer to Figure 21-3 and Table 21-5.
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Figure 21-3. Parallel Programming Timing, Read Sequence
NCMD RDY
2 3
12 13
NOE NVALID 4 DATA[15:0] 1 MODE[3:0] ADDR Adress IN
5 7 6 Z 8
9 11 10 X IN
Data OUT
Table 21-5.
Step 1 2 3 4 5 6 7 8 9 10 11 12 13
Read Handshake
Programmer Action Sets MODE and DATA signals Clears NCMD signal Waits for RDY low Sets DATA signal in tristate Clears NOE signal Waits for NVALID low Sets DATA bus in output mode and outputs the flash contents. Clears NVALID signal Reads value on DATA Bus Sets NOE signal Waits for NVALID high Sets DATA in ouput mode Sets NCMD signal Waits for RDY high Sets DATA bus in input mode Sets NVALID signal Waits for NCMD high Sets RDY signal Waits for NOE high Device Action Waits for NCMD low Latch MODE and DATA Clears RDY signal Waits for NOE Low DATA I/O Input Input Input Input Tristate Output Output Output Output X Input Input Input
21.2.5
Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 21-3 on page 117. Each command is driven by the programmer through the parallel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash.
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21.2.5.1
Flash Read Command This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 21-6.
Step 1 2 3 4 5 6 7 ... n n+1 n+2 n+3 n+4 n+5 ...
Read Command
MODE[3:0] CMDE ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... DATA[15:0] READ 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ... 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ...
Handshake Sequence Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Read handshaking Read handshaking ... Write handshaking Write handshaking Write handshaking Write handshaking Read handshaking Read handshaking ...
21.2.5.2
Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash: * before access to any page other than the current one * when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 21-7.
Step 1 2 3 4 5 6
Write Command
MODE[3:0] CMDE ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA[15:0] WP or WPL or EWP or EWPL 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++
Handshake Sequence Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking
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Table 21-7.
Step 7 ... n n+1 n+2 n+3 n+4 n+5 ...
Write Command (Continued)
MODE[3:0] DATA ... ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... DATA[15:0] *Memory Address++ ... 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ...
Handshake Sequence Write handshaking ... Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking ...
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. 21.2.5.3 Flash Full Erase Command This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 21-8.
Step 1 2
Full Erase Command
MODE[3:0] CMDE DATA DATA[15:0] EA 0
Handshake Sequence Write handshaking Write handshaking
21.2.5.4
Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated. In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the EA command.
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Table 21-9.
Step 1 2
Set and Clear Lock Bit Command
MODE[3:0] CMDE DATA DATA[15:0] SLB or CLB Bit Mask
Handshake Sequence Write handshaking Write handshaking
Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set.. Table 21-10. Get Lock Bit Command
Step 1 2 Handshake Sequence Write handshaking Read handshaking MODE[3:0] CMDE DATA DATA[15:0] GLB Lock Bit Mask Status 0 = Lock bit is cleared 1 = Lock bit is set
21.2.5.5
Flash General-purpose NVM Commands General-purpose NVM bits (GP NVM bits) can be set using the Set Fuse command (SFB). This command also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first GP NVM bit is activated. In the same way, the Clear Fuse command (CFB) is used to clear general-purpose NVM bits. All the general-purpose NVM bits are also cleared by the EA command. The general-purpose NVM bit is deactived when the corresponding bit in the pattern value is set to 1. Table 21-11. Set/Clear GP NVM Command
Step 1 2 Handshake Sequence Write handshaking Write handshaking MODE[3:0] CMDE DATA DATA[15:0] SFB or CFB GP NVM bit pattern value
General-purpose NVM bits can be read using the Get Fuse Bit command (GFB). The nth GP NVM bit is active when bit n of the bit mask is set.. Table 21-12. Get GP NVM Bit Command
Step 1 2 Handshake Sequence Write handshaking Read handshaking MODE[3:0] CMDE DATA DATA[15:0] GFB GP NVM Bit Mask Status 0 = GP NVM bit is cleared 1 = GP NVM bit is set
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21.2.5.6 Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. Table 21-13. Set Security Bit Command
Step 1 2 Handshake Sequence Write handshaking Write handshaking MODE[3:0] CMDE DATA DATA[15:0] SSE 0
21.2.5.7
Memory Read Command This command (RRAM) is used to perform a read access to any memory location. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 21-14. Read Command
Step 1 2 3 4 5 6 7 ... n n+1 n+2 n+3 n+4 n+5 ... Handshake Sequence Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Read handshaking Read handshaking ... Write handshaking Write handshaking Write handshaking Write handshaking Read handshaking Read handshaking ... MODE[3:0] CMDE ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... DATA[15:0] RRAM 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ... 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ...
21.2.5.8
Memory Write Command This command is used to perform a write access to any memory location. The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased.
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Table 21-15. Write Command
Step 1 2 3 4 5 6 7 ... n n+1 n+2 n+3 n+4 n+5 ... Handshake Sequence Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking ... Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking ... MODE[3:0] CMDE ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... DATA[15:0] WRAM 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ... 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ...
21.2.5.9
Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 21-16. Get Version Command
Step 1 2 Handshake Sequence Write handshaking Write handshaking MODE[3:0] CMDE DATA DATA[15:0] GVE Version
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21.3 Serial Fast Flash Programming
The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 "Standard Test Access Port and Boundary-Scan Architecture". Refer to this standard for an explanation of terms used in this chapter and for a description of the TAP controller states. In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG interface of the device. 21.3.1 Device Configuration In Serial Fast Flash Programming Mode, the device is in a specific test mode. Only a distinct set of pins is significant. Other pins must be left unconnected. Figure 21-4. Serial Programming
VDDIO VDDIO VDDIO GND TDI TDO TMS TCK TST PGMEN0 PGMEN1 PGMEN2
VDDCORE VDDIO VDDPLL VDDFLASH GND
0-50MHz
XIN
Table 21-17. Signal Description List
Signal Name Function Power VDDFLASH VDDIO VDDCORE VDDPLL GND Flash Power Supply I/O Lines Power Supply Core Power Supply PLL Power Power Supply Ground Clocks Main Clock Input. This input can be tied to GND. In this case, the device is clocked by the internal RC oscillator. Power Power Power Power Ground Type Active Level Comments
XIN
Input
32 kHz to 50 MHz
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Table 21-17. Signal Description List (Continued)
Signal Name Function Test TST PGMEN0 PGMEN1 PGMEN2 Test Mode Select Test Mode Select Test Mode Select Test Mode Select JTAG TCK TDI TDO TMS JTAG TCK JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select Input Input Output Input Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Input Input Input Input High High High Low Must be connected to VDDIO. Must be connected to VDDIO Must be connected to VDDIO Must be connected to GND Type Active Level Comments
21.3.2
Entering Serial Programming Mode The following algorithm puts the device in Serial Programming Mode: * Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL. * Apply XIN clock within TPOR_RESET + 32(TSCLK) if an external clock is available. * Wait for TPOR_RESET. * Reset the TAP controller clocking 5 TCK pulses with TMS set. * Shift 0x2 into the IR register ( IR is 4 bits long, LSB first) without going through the Run-TestIdle state. * Shift 0x2 into the DR register ( DR is 4 bits long, LSB first) without going through the RunTest-Idle state. * Shift 0xC into the IR register ( IR is 4 bits long, LSB first) without going through the Run-TestIdle state.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32 kHz) is connected to XIN, then the device will switch on the external clock. Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer handshake.
Table 21-18. Reset TAP controller and go to Select-DR-Scan
TDI X X X X X X Xt TMS 1 1 1 1 1 0 1 Test-Logic Reset Run-Test/Idle Select-DR-Scan TAP Controller State
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21.3.3 Read/Write Handshake Two registers of the device are accessible through the JTAG: * Debug Comms Control Register: DCCR * Debug Comms Data Register: DCDR Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data. The 32-bit data field is ignored. Figure 21-5. TAP 8-bit DR Register
TDI r/w 4 Address 5 0 31 Data 32 0 TDO
Address Decoder
Debug Comms Control Register Debug Comms Control Register
A read or write takes place when the TAP controller enters UPDATE-DR state. * The address of the Debug Comms Control Register is 0x04. * The address of the Debug Comms Data Register is 0x05. The Debug Comms Control Register is read-only and allows synchronized handshaking between the processor and the debugger. * Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms Data Register. If the device is busy W = 0, then the programmer must poll until W = 1. * Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data Register. If R = 1, data previously placed there through the scan chain has not been collected by the device and so the programmer must wait. 21.3.4 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 21-3 on page 117. Commands are run by the programmer through the serial interface that is reading and writing the Debug Comms Registers. 21.3.4.1 Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at
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any valid address in the memory plane. This address must be word-aligned. The address is automatically incremented. Table 21-19. Read Command
Read/Write Write Write Read Read ... Read DR Data (Number of Words to Read) << 16 | READ Address Memory [address] Memory [address+4] ... Memory [address+(Number of Words to Read - 1)* 4]
21.3.4.2
Flash Write Command This command is used to write the Flash contents. The address transmitted must be a valid Flash address in the memory plane. The Flash memory plane is organized into several pages. Data to be written is stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash: * before access to any page than the current one * at the end of the number of words transmitted The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 21-20. Write Command
Read/Write Write Write Write Write Write Write DR Data (Number of Words to Write) << 16 | (WP or WPL or EWP or EWPL) Address Memory [address] Memory [address+4] Memory [address+8] Memory [address+(Number of Words to Write - 1)* 4]
Flash Write Page and Lock command (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. Flash Erase Page and Write command (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL commands.
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21.3.4.3 Flash Full Erase Command This command is used to erase the Flash memory planes. All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command. Table 21-21. Full Erase Command
Read/Write Write DR Data EA
21.3.4.4
Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the first lock bit and so on. In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits can also be cleared by the EA command. Table 21-22. Set and Clear Lock Bit Command
Read/Write Write Write DR Data SLB or CLB Bit Mask
Lock bits can be read using Get Lock Bit command (GLB). When a bit set in the Bit Mask is returned, then the corresponding lock bit is active. Table 21-23. Get Lock Bit Command
Read/Write Write Read DR Data GLB Bit Mask
21.3.4.5
Flash General-purpose NVM Commands General-purpose NVM bits (GP NVM) can be set with the Set Fuse command (SFB). Using this command, several GP NVM bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the first fuse bit and so on. In the same way, the Clear Fuse command (CFB) is used to clear GP NVM bits. All the generalpurpose NVM bits are also cleared by the EA command. Table 21-24. Set and Clear General-purpose NVM Bit Command
Read/Write Write Write DR Data SFB or CFB Bit Mask
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GP NVM bits can be read using Get Fuse Bit command (GFB). When a bit set in the Bit Mask is returned, then the corresponding fuse bit is set. Table 21-25. Get General-purpose NVM Bit Command
Read/Write Write Read DR Data GFB Bit Mask
21.3.4.6
Flash Security Bit Command Security bits can be set using Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. Only an event on the Erase pin can erase the security bit once the contents of the Flash have been erased. Table 21-26. Set Security Bit Command
Read/Write Write DR Data SSE
21.3.4.7
Memory Read Command This command is used to perform a read access to any memory location. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. An internal address buffer is automatically increased. Table 21-27. Read Command
Read/Write Write Write Read Read ... Read DR Data (Number of Words to Read) << 16 | RRAM Address Memory [address] Memory [address+4] ... Memory [address+(Number of Words to Read - 1)* 4]
21.3.4.8
Memory Write Command This command is used to perform a write access to any memory location. The Memory Wrire command (WRAM) is optimized for consecutive writes. An internal address buffer is automatically increased. Table 21-28. Write Command
Read/Write Write Write Write DR Data (Number of Words to Write) << 16 | (WRAM) Address Memory [address]
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Table 21-28. Write Command
Read/Write Write Write Write DR Data Memory [address+4] Memory [address+8] Memory [address+(Number of Words to Write - 1)* 4]
21.3.4.9
Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 21-29. Get Version Command
Read/Write Write Read DR Data GVE Version
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22. AT91SAM Boot Program
22.1 Description
The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BATM Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port.
22.2
Flow Diagram
The Boot Program implements the algorithm in Figure 22-1.
Figure 22-1. Boot Program Algorithm Flow Diagram
AutoBaudrate Sequence Device Setup OR USB Enumeration Successful
Run SAM-BA Boot
Run SAM-BA Boot
22.3
Device Initialization
Initialization follows the steps described below: 1. FIQ initialization 1. Stack setup for ARM supervisor mode 2. Setup the Embedded Flash Controller 3. External Clock detection 4. Main oscillator frequency detection if no external clock detected 5. Switch Master Clock on Main Oscillator 6. Copy code into SRAM 7. C variable initialization 8. PLL setup: PLL is initialized to generate a 48 MHz clock necessary to use the USB Device 9. Disable of the Watchdog and enable of the user reset 10. Initialization of the USB Device Port 11. Jump to SAM-BA Boot sequence (see "SAM-BA Boot" on page 133)
22.4
SAM-BA Boot
The SAM-BA boot principle is to: - Wait for USB Device enumeration - Execute the AutoBaudrate sequence in parallel (see Figure 22-2)
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Figure 22-2. AutoBaudrate Flow Diagram
Device Setup
Character '0x80' received ? Yes
No
1st measurement
Character '0x80' received ? Yes Character '#' received ? Yes
No
2nd measurement
No
Test Communication
Send Character '>'
UART operational
Run SAM-BA Boot
- Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in Table 22-1. Table 22-1.
Command O o H h W w S R G V
Commands Available through the SAM-BA Boot
Action write a byte read a byte write a half word read a half word write a word read a word send a file receive a file go display version Argument(s) Address, Value# Address,# Address, Value# Address,# Address, Value# Address,# Address,# Address, NbOfBytes# Address# No argument Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# R200000,1234# G200200# V#
* Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. - Address: Address in hexadecimal. - Value: Byte, halfword or word to write in hexadecimal. - Output: `>'.
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* Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. - Address: Address in hexadecimal - Output: The byte, halfword or word read in hexadecimal following by `>' * Send a file (S): Send a file to a specified address - Address: Address in hexadecimal - Output: `>'.
Note: There is a time-out on this command which is reached when the prompt `>' appears before the end of the command execution.
* Receive a file (R): Receive data into a file from a specified address - Address: Address in hexadecimal - NbOfBytes: Number of bytes in hexadecimal to receive - Output: `>' * Go (G): Jump to a specified address and execute the code - Address: Address to jump in hexadecimal - Output: `>' * Get Version (V): Return the SAM-BA boot version - Output: `>' 22.4.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 22.4.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: <255-blk #><--128 data bytes--> in which: - = 01 hex - = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) - <255-blk #> = 1's complement of the blk#. - = 2 bytes CRC16 Figure 22-3 shows a transmission using this protocol.
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Figure 22-3. Xmodem Transfer Example
Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device
22.4.3
USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows(R), from Windows 98SE to Windows XP. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel's vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document "USB Basic Application", literature number 6123, for more details.
22.4.3.1
Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 22-2.
Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION
Handled Standard Requests
Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value.
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Table 22-2.
Request GET_STATUS SET_FEATURE CLEAR_FEATURE
Handled Standard Requests (Continued)
Definition Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature.
The device also handles some class requests defined in the CDC class. Table 22-3.
Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE
Handled Class Requests
Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present.
Unhandled requests are STALLed. 22.4.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response.
22.5
Hardware and Software Constraints
* SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available size for the user code is 57344 bytes for AT91SAM7X256 and 24576 bytes for AT91SAM7X128. * USB requirements: - 18.432 MHz Quartz Table 22-4.
Device AT91SAM7X256 AT91SAM7X128
User Area Addresses
Start Address 0x202000 0x202000 End Address 0x210000 0x208000 Size (bytes) 57344 24576
Table 22-5.
Peripheral DBGU DBGU
Pins Driven during Boot Program Execution
Pin DRXD DTXD PIO Line PA27 PA28
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23. Peripheral DMA Controller (PDC)
23.1 Overview
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Contoller avoids processor intervention and removes the processor interrupt-handling overhead. This significantly reduces the number of clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and makes it more power efficient. The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each UART, USART, SSC and SPI. The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains: * A 32-bit memory pointer register * A 16-bit transfer count register * A 32-bit register for next memory pointer * A 16-bit register for next transfer count The peripheral triggers PDC transfers using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral.
23.2
Block Diagram
Figure 23-1. Block Diagram
Peripheral Peripheral DMA Controller
THR
PDC Channel 0
RHR
PDC Channel 1
Control
Memory Controller
Control
Status & Control
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23.3
23.3.1
Functional Description
Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four 16-bit Counter Registers (RCR, RNCR, TCR, and TNCR). The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel. The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register. These control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads. The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX, RXBUFF, and TXBUFE). ENDRX flag is set when the PERIPH_RCR register reaches zero. RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero. ENDTX flag is set when the PERIPH_TCR register reaches zero. TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the peripheral status register.
23.3.2
Memory Pointers Each peripheral is connected to the PDC by a receiver data channel and a transmitter data channel. Each channel has an internal 32-bit memory pointer. Each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory). Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4, respectively for peripheral transfers. If a memory pointer is reprogrammed while the PDC is in operation, the transfer address is changed, and the PDC performs transfers using the new address.
23.3.3
Transfer Counters There is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. These counters are decremented after each data transfer. When the counter reaches zero, the transfer is complete and the PDC stops transferring data. If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag.
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If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to re-enable the triggers. For each channel, two status bits indicate the end of the current buffer (ENDRX, ENTX) and the end of both current and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can trigger an interrupt request to the AIC. The peripheral end flag is automatically cleared when one of the counter-registers (Counter or Next Counter Register) is written. Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero. 23.3.4 Data Transfers The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals. When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then requests access to the system bus. When access is granted, the PDC starts a read of the peripheral Receive Holding Register (RHR) and then triggers a write in the memory. After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decremented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops. The same procedure is followed, in reverse, for transmit transfers. 23.3.5 Priority of PDC Transfer Requests The Peripheral DMA Controller handles transfer requests from the channel according to priorities fixed for each product.These priorities are defined in the product datasheet. If simultaneous requests of the same type (receiver or transmitter) occur on identical peripherals, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests.
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23.4
Peripheral DMA Controller (PDC) User Interface
Peripheral DMA Controller (PDC) Register Mapping
Register Receive Pointer Register Receive Counter Register Transmit Pointer Register Transmit Counter Register Receive Next Pointer Register Receive Next Counter Register Transmit Next Pointer Register Transmit Next Counter Register PDC Transfer Control Register PDC Transfer Status Register Register Name PERIPH(1)_RPR PERIPH_RCR PERIPH_TPR PERIPH_TCR PERIPH_RNPR PERIPH_RNCR PERIPH_TNPR PERIPH_TNCR PERIPH_PTCR PERIPH_PTSR Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Read-only Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Table 23-1.
Offset
0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 Note:
1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc).
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23.4.1 PDC Receive Pointer Register
PERIPH_RPR
Register Name: Access Type:
31
Read/Write
30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
7 6 5 4 3 2 1 0
RXPTR
* RXPTR: Receive Pointer Address Address of the next receive transfer.
23.4.2
PDC Receive Counter Register
PERIPH_RCR
Register Name: Access Type:
31
Read/Write
30 29 28 27 26 25 24
-23 22 21 20 19 18 17 16
-15 14 13 12 11 10 9 8
RXCTR
7 6 5 4 3 2 1 0
RXCTR
* RXCTR: Receive Counter Value Number of receive transfers to be performed.
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23.4.3
PDC Transmit Pointer Register
PERIPH_TPR
Register Name: Access Type:
31
Read/Write
30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
7 6 5 4 3 2 1 0
TXPTR
* TXPTR: Transmit Pointer Address Address of the transmit buffer.
23.4.4
PDC Transmit Counter Register
PERIPH_TCR
Register Name: Access Type:
31
Read/Write
30 29 28 27 26 25 24
-23 22 21 20 19 18 17 16
-15 14 13 12 11 10 9 8
TXCTR
7 6 5 4 3 2 1 0
TXCTR
* TXCTR: Transmit Counter Value TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral DMA transfer is stopped.
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23.4.5 PDC Receive Next Pointer Register
PERIPH_RNPR
Register Name: Access Type:
31
Read/Write
30 29 28 27 26 25 24
RXNPTR
23 22 21 20 19 18 17 16
RXNPTR
15 14 13 12 11 10 9 8
RXNPTR
7 6 5 4 3 2 1 0
RXNPTR
* RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when the current buffer is full.
23.4.6
PDC Receive Next Counter Register
PERIPH_RNCR
Register Name: Access Type:
31
Read/Write
30 29 28 27 26 25 24
-23 22 21 20 19 18 17 16
-15 14 13 12 11 10 9 8
RXNCR
7 6 5 4 3 2 1 0
RXNCR
* RXNCR: Receive Next Counter Value RXNCR is the size of the next buffer to receive.
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23.4.7
PDC Transmit Next Pointer Register
PERIPH_TNPR
Register Name: Access Type:
31
Read/Write
30 29 28 27 26 25 24
TXNPTR
23 22 21 20 19 18 17 16
TXNPTR
15 14 13 12 11 10 9 8
TXNPTR
7 6 5 4 3 2 1 0
TXNPTR
* TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer is empty.
23.4.8
PDC Transmit Next Counter Register
PERIPH_TNCR
Register Name: Access Type:
31
Read/Write
30 29 28 27 26 25 24
-23 22 21 20 19 18 17 16
-15 14 13 12 11 10 9 8
TXNCR
7 6 5 4 3 2 1 0
TXNCR
* TXNCR: Transmit Next Counter Value TXNCR is the size of the next buffer to transmit.
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23.4.9 PDC Transfer Control Register
PERIPH_PTCR
Register Name: Access Type:
31
Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
TXTDIS
1
TXTEN
0
-
-
-
-
-
-
RXTDIS
RXTEN
* RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables the receiver PDC transfer requests if RXTDIS is not set. * RXTDIS: Receiver Transfer Disable 0 = No effect. 1 = Disables the receiver PDC transfer requests. * TXTEN: Transmitter Transfer Enable 0 = No effect. 1 = Enables the transmitter PDC transfer requests. * TXTDIS: Transmitter Transfer Disable 0 = No effect. 1 = Disables the transmitter PDC transfer requests
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23.4.10
PDC Transfer Status Register
PERIPH_PTSR
Register Name: Access Type:
31
Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
TXTEN
0
-
-
-
-
-
-
-
RXTEN
* RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. 1 = Receiver PDC transfer requests are enabled. * TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled. 1 = Transmitter PDC transfer requests are enabled.
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24. Advanced Interrupt Controller (AIC)
24.1 Overview
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or highlevel or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt.
24.2
Block Diagram
Figure 24-1. Block Diagram
FIQ IRQ0-IRQn AIC ARM Processor Up to Thirty-two Sources nFIQ nIRQ
Embedded PeripheralEE Embedded
Peripheral Embedded
Peripheral
APB
24.3
Application Block Diagram
Figure 24-2. Description of the Application Block
OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller Embedded Peripherals External Peripherals (External Interrupts)
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24.4
AIC Detailed Block Diagram
Figure 24-3. AIC Detailed Block Diagram
Advanced Interrupt Controller FIQ PIO Controller External Source Input Stage Fast Interrupt Controller ARM Processor nFIQ
nIRQ IRQ0-IRQn PIOIRQ Internal Source Input Stage Fast Forcing Interrupt Priority Controller Processor Clock Power Management Controller User Interface Wake Up
Embedded Peripherals
APB
24.5
I/O Line Description
Table 24-1.
Pin Name FIQ IRQ0 - IRQn
I/O Line Description
Pin Description Fast Interrupt Interrupt 0 - Interrupt n Type Input Input
24.6
24.6.1
Product Dependencies
I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path.
24.6.2
Power Management The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
24.6.3
Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used.
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The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines, such as the System Timer, the Real Time Clock, the Power Management Controller and the Memory Controller. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.
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24.7
24.7.1
Functional Description
Interrupt Source Control Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes.
24.7.1.1
24.7.1.2
Interrupt Source Enabling Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts.
24.7.1.3
Interrupt Clearing and Setting All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-sensitive mode has no effect. The clear operation is perfunctory, as the software must perform an action to reinitialize the "memorization" circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See "Priority Controller" on page 155.) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as an FIQ source. (See "Fast Forcing" on page 159.) The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.
24.7.1.4
Interrupt Status For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not. The AIC_ISR register reads the number of the current interrupt (see "Priority Controller" on page 155) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems.
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24.7.1.5 Internal Interrupt Source Input Stage Figure 24-4. Internal Interrupt Source Input Stage
AIC_SMRI (SRCTYPE) Source i Level/ Edge AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR
Edge
Detector Set Clear AIC_ISCR AIC_ICCR FF
AIC_IDCR
24.7.1.6
External Interrupt Source Input Stage Figure 24-5. External Interrupt Source Input Stage
AIC_SMRi SRCTYPE Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Pos./Neg. Edge Detector Set AIC_ISCR AIC_ICCR Clear AIC_IDCR AIC_IECR
High/Low
FF
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24.7.2
Interrupt Latencies Global interrupt latencies depend on several parameters, including: * The time the software masks the interrupts. * Occurrence, either at the processor level or at the AIC level. * The execution time of the instruction in progress when the interrupt occurs. * The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.
24.7.2.1
External Interrupt Edge Triggered Source Figure 24-6. External Interrupt Edge Triggered Source
MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge)
nIRQ Maximum IRQ Latency = 4 Cycles
nFIQ Maximum FIQ Latency = 4 Cycles
24.7.2.2
External Interrupt Level Sensitive Source Figure 24-7. External Interrupt Level Sensitive Source
MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles
nFIQ Maximum FIQ Latency = 3 cycles
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24.7.2.3 Internal Interrupt Edge Triggered Source Figure 24-8. Internal Interrupt Edge Triggered Source
MCK
nIRQ
Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active
24.7.2.4
Internal Interrupt Level Sensitive Source Figure 24-9. Internal Interrupt Level Sensitive Source
MCK
nIRQ
Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active
24.7.3 24.7.3.1
Normal Interrupt Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SVR (Source Vector Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in 155
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progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 24.7.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 24.7.3.3 Interrupt Vectoring The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system's general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 24.7.3.4 Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits. It is assumed that:
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1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit "I" of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: - Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. - De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. - Automatically clears the interrupt, if it has been programmed to be edge-triggered. - Pushes the current level and the current interrupt number on to the stack. - Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the "I" bit in CPSR, allowing reassertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1.
Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.
7. The "I" bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the "I" bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.
Note: The "I" bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked).
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24.7.4 24.7.4.1
Fast Interrupt Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to an FIQ pin of the product, either directly or through a PIO Controller.
24.7.4.2
Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.
24.7.4.3
Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. 24.7.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt:
LDR PC, [PC, # -&F20]
3. The user does not need nested fast interrupts. When nFIQ is asserted, if the bit "F" of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. 2. The ARM core enters FIQ mode.
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3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR.
Note: The "F" bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction. 24.7.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages. When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR). The Fast Interrupt Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not
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clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the fast forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. Figure 24-10. Fast Forcing
Source 0 _ FIQ Input Stage AIC_IMR AIC_IPR
Automatic Clear
nFIQ
Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR Source n Input Stage Automatic Clear AIC_IMR AIC_IPR Priority Manager nIRQ
Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n.
24.7.5
Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences: * If an enabled interrupt with a higher priority than the current one is pending, it is stacked. * If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to
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not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. 24.7.6 Spurious Interrupt The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: * An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. * An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) * An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 24.7.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution.
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24.8
24.8.1
Advanced Interrupt Controller (AIC) User Interface
Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only an 4-Kbyte offset.
Table 24-2.
Offset
0000 0x04 --0x7C 0x80 0x84 --0xFC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x144 0x148
Advanced Interrupt Controller (AIC) Register Mapping
Register
Source Mode Register 0 Source Mode Register 1 --Source Mode Register 31 Source Vector Register 0 Source Vector Register 1 --Source Vector Register 31 Interrupt Vector Register Fast Interrupt Vector Register Interrupt Status Register Interrupt Pending Register Interrupt Mask Register Core Interrupt Status Register Reserved Reserved Interrupt Enable Command Register Interrupt Disable Command Register Interrupt Clear Command Register Interrupt Set Command Register End of Interrupt Command Register Spurious Interrupt Vector Register Debug Control Register Reserved Fast Forcing Enable Register Fast Forcing Disable Register Fast Forcing Status Register
Name
AIC_SMR0 AIC_SMR1 --AIC_SMR31 AIC_SVR0 AIC_SVR1 --AIC_SVR31 AIC_IVR AIC_FVR AIC_ISR AIC_IPR AIC_IMR AIC_CISR ----AIC_IECR AIC_IDCR AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR --AIC_FFER AIC_FFDR AIC_FFSR
Access
Read/Write Read/Write --Read/Write Read/Write Read/Write --Read/Write Read-only Read-only Read-only Read-only Read-only Read-only ----Write-only Write-only Write-only Write-only Write-only Read/Write Read/Write --Write-only Write-only Read-only
Reset Value
0x0 0x0 --0x0 0x0 0x0 --0x0 0x0 0x0 0x0 0x0(1) 0x0 0x0 --------------0x0 0x0 ------0x0
Note: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending.
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24.8.2 AIC Source Mode Register AIC_SMR0..AIC_SMR31 Read/Write 0x0
30 - 22 - 14 - 6 SRCTYPE 29 - 21 - 13 - 5 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 PRIOR 24 - 16 - 8 - 0
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
* PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the related SMR register AIC_SMRx. * SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources.
SRCTYPE 0 0 1 1 0 1 0 1 Internal Interrupt Sources High level Sensitive Positive edge triggered High level Sensitive Positive edge triggered External Interrupt Sources Low level Sensitive Negative edge triggered High level Sensitive Positive edge triggered
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24.8.3
AIC Source Vector Register AIC_SVR0..AIC_SVR31 Read/Write 0x0
30 29 28 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type: Reset Value:
31
* VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.
24.8.4
AIC Interrupt Vector Register AIC_IVR Read-only 0
30 29 28 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type: Reset Value:
31
* IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU.
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24.8.5 AIC FIQ Vector Register AIC_FVR Read-only 0
30 29 28 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type: Reset Value:
31
* FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the Fast Interrupt Vector Register reads the value stored in AIC_SPU.
24.8.6
AIC Interrupt Status Register AIC_ISR Read-only 0
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 27 - 19 - 11 - 3 26 - 18 - 10 - 2 IRQID 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
* IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number.
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24.8.7
AIC Interrupt Pending Register AIC_IPR Read-only 0
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type: Reset Value:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is not pending. 1 = Corresponding interrupt is pending.
24.8.8
AIC Interrupt Mask Register AIC_IMR Read-only 0
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type: Reset Value:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled.
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24.8.9 AIC Core Interrupt Status Register AIC_CISR Read-only 0
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 NIRQ 24 - 16 - 8 - 0 NIFQ
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
* NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. * NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active.
24.8.10
AIC Interrupt Enable Command Register AIC_IECR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID3: Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt.
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24.8.11
AIC Interrupt Disable Command Register AIC_IDCR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt.
24.8.12
AIC Interrupt Clear Command Register AIC_ICCR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt.
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24.8.13 AIC Interrupt Set Command Register AIC_ISCR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt.
24.8.14
AIC End of Interrupt Command Register AIC_EOICR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 -
Register Name: Access Type:
31 - 23 - 15 - 7 -
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment.
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24.8.15
AIC Spurious Interrupt Vector Register AIC_SPU Read/Write 0
30 29 28 SIQV 27 26 25 24
Register Name: Access Type: Reset Value:
31
23
22
21
20 SIQV
19
18
17
16
15
14
13
12 SIQV
11
10
9
8
7
6
5
4 SIQV
3
2
1
0
* SIQV: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
24.8.16
AIC Debug Control Register AIC_DEBUG Read/Write 0
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 GMSK 24 - 16 - 8 - 0 PROT
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
* PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled. * GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state.
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24.8.17 AIC Fast Forcing Enable Register AIC_FFER Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 -
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* SYS, PID2-PID31: Fast Forcing Enable 0 = No effect. 1 = Enables the fast forcing feature on the corresponding interrupt.
24.8.18
AIC Fast Forcing Disable Register AIC_FFDR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 -
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* SYS, PID2-PID31: Fast Forcing Disable 0 = No effect. 1 = Disables the Fast Forcing feature on the corresponding interrupt.
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AIC Fast Forcing Status Register AIC_FFSR Read-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 -
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt. 1 = The Fast Forcing feature is enabled on the corresponding interrupt.
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25. Clock Generator
25.1 Description
The Clock Generator is made up of 1 PLL, a Main Oscillator, and an RC Oscillator. It provides the following clocks: * SLCK, the Slow Clock, which is the only permanent clock within the system * MAINCK is the output of the Main Oscillator * PLLCK is the output of the Divider and PLL block The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 26.9. However, the Clock Generator registers are named CKGR_.
25.2
Slow Clock RC Oscillator
The slow clock is the output of the RC Oscillator and is the only clock considered permanent in a system that includes the Power Management Controller. It is mandatory in the operations of the PMC. The user has to take the possible drifts of the RC Oscillator into account. More details are given in the DC Characteristics section of the product datasheet.
25.3
Main Oscillator
Figure 25-1 shows the Main Oscillator block diagram.
Figure 25-1. Main Oscillator BlockD iagram
MOSCEN
XIN XOUT
Main Oscillator
MAINCK Main Clock
OSCOUNT
SLCK Slow Clock
Main Oscillator Counter Main Clock Frequency Counter
MOSCS
MAINF MAINRDY
25.3.1
Main Oscillator Connections The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 25-2. The 1 k resistor is only required for crystals with frequencies lower than 8 MHz. The oscillator contains 25 pF capacitors on each XIN and XOUT pin. Consequently, CL1 and CL2 can be removed when a
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crystal with a load capacitance of 12.5 pF is used. For further details on the electrical characteristics of the Main Oscillator, see the DC Characteristics section of the product datasheet. Figure 25-2. Typical Crystal Connection
XIN XOUT GND
1K
CL1
CL2
25.3.2
Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises. Main Oscillator Control To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR). When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is automatically cleared, indicating the main clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main oscillator. When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor.
25.3.3
25.3.4
Main Clock Frequency Counter The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency connected to the Main Oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. The Main Clock frequency counter starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock
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cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. 25.3.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.
25.4
Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider. Figure 25-3 shows the block diagram of the divider and PLL block.
Figure 25-3. Divider and PLL Block Diagram
DIV MUL OUT
MAINCK
Divider
PLL
PLLCK
PLLRC PLLCOUNT
SLCK
PLL Counter
LOCK
25.4.1
PLL Filter The PLL requires connection to an external second-order filter through the PLLRC pin. Figure 25-4 shows a schematic of these filters.
Figure 25-4. PLL Capacitors and Resistors
PLLRC PLL
R
C2 C1 GND
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time.
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25.4.2 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLL allows multiplication of the divider's outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_PLLR are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel.
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26. Power Management Controller (PMC)
26.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: * MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the AIC and the Memory Controller. * Processor Clock (PCK), switched off when entering processor in idle mode. * Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet. * UDP Clock (UDPCK), required by USB Device Port operations. * Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins.
26.2
Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLL. The Master Clock Controller is made up of a clock selector and a prescaler. The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a highspeed clock to a lower one to inform the software when the change is actually done.
Figure 26-1. Master Clock Controller
PMC_MCKR CSS PMC_MCKR PRES
SLCK MAINCK PLLCK To the Processor Clock Controller (PCK) Master Clock Prescaler MCK
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26.3 Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be enabled and disabled by writing the System Clock Enable (PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus.
26.4
USB Clock Controller
The USB Source Clock is the PLL output. If using the USB, the user must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of 0.25% depending on the USBDIV bit in CKGR_PLLR. When the PLL output is stable, i.e., the LOCK bit is set:
* The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may be controlled via the Peripheral Clock Controller. Figure 26-2. USB Clock Controller
USBDIV USB Source Clock
Divider /1,/2,/4
UDP Clock (UDPCK)
UDP
26.5
Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR). When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system.
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The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.
26.6
Programmable Clock Output Controller
The PMC controls 4 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register). Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed.
26.7
Programming Sequence
1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR register. Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register.
Code Example:
write_register(CKGR_MOR,0x00000701)
Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles. So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles.
2. Checking the Main Oscillator Frequency (Optional): In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles.
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3. Setting PLL and divider: All parameters needed to configure PLL and the divider are located in the CKGR_PLLR register. The DIV field is used to control divider itself. A value between 0 and 255 can be programmed. Divider output is divider input divided by DIV parameter. By default DIV parameter is set to 0 which means that divider is turned off. The OUT field is used to select the PLL B output frequency range. The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input frequency multiplied by (MUL + 1). The PLLCOUNT field specifies the number of slow clock cycles before LOCK bit is set in the PMC_SR register after CKGR_PLLR register has been written. Once the PMC_PLL register has been written, the user must wait for the LOCK bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCK has been enabled in the PMC_IER register. All parameters in CKGR_PLLR can be programmed in a single write operation. If at some stage one of the following parameters, MUL, DIV is modified, LOCK bit will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is constrained to wait for LOCK bit to be set before using the PLL output clock. The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s).
Code Example:
write_register(CKGR_PLLR,0x00040805)
If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is PLL input clock multiplied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after eight slow clock cycles.
4. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow clock. The PRES field is used to control the Master Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES parameter is set to 1 which means that master clock is equal to slow clock. Once PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register.
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All parameters in PMC_MCKR can be programmed in a single write operation. If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks.
Note:
IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see Section 26.8.2. "Clock Switching Waveforms" on page 183.
Code Example:
write_register(PMC_MCKR,0x00000011)
The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 5. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 4 programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled. PMC_PCKx registers are used to configure Programmable clocks. The CSS field is used to select the programmable clock divider source. Four clock options are available: main clock, slow clock, PLLCK. By default, the clock source selected is slow clock. The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock. Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set.
Code Example:
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write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32. 6. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER and PMC_PCDR. Depending on the system used, 15 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled.
Note:
Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
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26.8
26.8.1
Clock Switching Details
Master Clock Switching Timings Table 26-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 26-1. Clock Switching Timings (Worst Case)
Main Clock SLCK PLL Clock
From To Main Clock
- 0.5 x Main Clock + 4.5 x SLCK 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock
4 x SLCK + 2.5 x Main Clock - 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK
3 x PLL Clock + 4 x SLCK + 1 x Main Clock 3 x PLL Clock + 5 x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK
SLCK
PLL Clock
26.8.2
Clock Switching Waveforms
Figure 26-3. Switch Master Clock from Slow Clock to PLL Clock
Slow Clock
PLL Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
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Figure 26-4. Switch Master Clock from Main Clock to Slow Clock
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
Figure 26-5. Change PLL Programming
Main Clock
PLL Clock
LOCK
MCKRDY
Master Clock Main Clock Write CKGR_PLLR
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Figure 26-6. Programmable Clock Output Programming
PLL Clock
PCKRDY
PCKx Output
Write PMC_PCKx
PLL Clock is selected
Write PMC_SCER
PCKx is enabled
Write PMC_SCDR
PCKx is disabled
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26.9 Power Management Controller (PMC) User Interface
Register Mapping
Register System Clock Enable Register System Clock Disable Register System Clock Status Register Reserved Peripheral Clock Enable Register Peripheral Clock Disable Register Peripheral Clock Status Register Reserved Main Oscillator Register Main Clock Frequency Register Reserved PLL Register Master Clock Register Application Clock Register Reserved Reserved Programmable Clock 0 Register Programmable Clock 1 Register ... Interrupt Enable Register Interrupt Disable Register Status Register Name PMC_SCER PMC_SCDR PMC _SCSR - PMC _PCER PMC_PCDR PMC_PCSR - CKGR_MOR CKGR_MCFR - CKGR_PLLR PMC_MCKR PMC_ACKR - - PMC_PCK0 PMC_PCK1 ... PMC_IER PMC_IDR PMC_SR ... Write-only Write-only Read-only Access Write-only Write-only Read-only - Write-only Write-only Read-only - Read/Write Read-only - Read/Write Read/Write Read/Write - - Read/Write Read/Write ... --0x08 Reset Value - - 0x01 - - - 0x0 - 0x0 0x0 - 0x3F00 0x0 0x0 - - 0x0 0x0
Table 26-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 ... 0x0060 0x0064 0x0068
0x006C 0x0070 - 0x00FC
Interrupt Mask Register Reserved
PMC_IMR -
Read-only -
0x0 -
186
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26.9.1 PMC System Clock Enable Register PMC_SCER Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCK3
3
PCK2
2
PCK1
1
PCK0
0
UDP
-
-
-
-
-
-
PCK
* PCK: Processor Clock Enable 0 = No effect. 1 = Enables the Processor clock. * UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port. * PCKx: Programmable Clock x Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output.
187
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26.9.2 PMC System Clock Disable Register PMC_SCDR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCK3
3
PCK2
2
PCK1
1
PCK0
0
UDP
-
-
-
-
-
-
PCK
* PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter teh processor in Idle Mode. * UDP: USB Device Port Clock Disable 0 = No effect. 1 = Disables the 48 MHz clock of the USB Device Port. * PCKx: Programmable Clock x Output Disable 0 = No effect. 1 = Disables the corresponding Programmable Clock output.
188
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26.9.3 PMC System Clock Status Register PMC_SCSR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCK3
3
PCK2
2
PCK1
1
PCK0
0
UDP
-
-
-
-
-
-
PCK
* PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled. * UDP: USB Device Port Clock Status 0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled. 1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled. * PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled.
189
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26.9.4 PMC Peripheral Clock Enable Register PMC_PCER Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
PID31
23
PID30
22
PID29
21
PID28
20
PID27
19
PID26
18
PID25
17
PID24
16
PID23
15
PID22
14
PID21
13
PID20
12
PID19
11
PID18
10
PID17
9
PID16
8
PID15
7
PID14
6
PID13
5
PID12
4
PID11
3
PID10
2
PID9
1
PID8
0
PID7
PID6
PID5
PID4
PID3
PID2
-
-
* PIDx: Peripheral Clock x Enable 0 = No effect. 1 = Enables the corresponding peripheral clock.
Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
26.9.5
PMC Peripheral Clock Disable Register PMC_PCDR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
PID31
23
PID30
22
PID29
21
PID28
20
PID27
19
PID26
18
PID25
17
PID24
16
PID23
15
PID22
14
PID21
13
PID20
12
PID19
11
PID18
10
PID17
9
PID16
8
PID15
7
PID14
6
PID13
5
PID12
4
PID11
3
PID10
2
PID9
1
PID8
0
PID7
PID6
PID5
PID4
PID3
PID2
-
-
* PIDx: Peripheral Clock x Disable 0 = No effect. 1 = Disables the corresponding peripheral clock.
190
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26.9.6 PMC Peripheral Clock Status Register PMC_PCSR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
PID31
23
PID30
22
PID29
21
PID28
20
PID27
19
PID26
18
PID25
17
PID24
16
PID23
15
PID22
14
PID21
13
PID20
12
PID19
11
PID18
10
PID17
9
PID16
8
PID15
7
PID14
6
PID13
5
PID12
4
PID11
3
PID10
2
PID9
1
PID8
0
PID7
PID6
PID5
PID4
PID3
PID2
-
-
* PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled.
191
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26.9.7 PMC Clock Generator Main Oscillator Register CKGR_MOR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 OSCOUNT 7 - 6 - 5 - 4 - 3 - 2 - 1 OSCBYPASS 0 MOSCEN 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0. When MOSCEN is set, the MOSCS flag is set once the Main Oscillator startup time is achieved. * OSCBYPASS: Oscillator Bypass 0 = No effect. 1 = The Main Oscillator is bypassed . MOSCEN must be set to 0. An external clock must be connected on XIN. When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set. Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag. * OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time.
192
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26.9.8 PMC Clock Generator Main Clock Frequency Register CKGR_MCFR Read-only
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 MAINF 7 6 5 4 MAINF 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 MAINRDY 8
Register Name: Access Type:
31 - 23 - 15
* MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. * MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled. 1 = The Main Oscillator has been enabled previously and MAINF value is available.
193
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26.9.9 PMC Clock Generator PLL Register CKGR_PLLR Read/Write
30 - 22 29 USBDIV 21 20 MUL 15 OUT 7 6 5 4 DIV 3 14 13 12 11 PLLCOUNT 2 1 0 10 9 8 28 27 - 19 26 25 MUL 17 24
Register Name: Access Type:
31 - 23
18
16
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. * DIV: Divider
DIV 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIV.
* PLLCOUNT: PLL Counter Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written. * OUT: PLL Clock Frequency Range
OUT 0 0 1 1 0 1 0 1 PLL Clock Frequency Range Refer to the DC Characteristics section of the product datasheet Reserved Refer to the DC Characteristics section of the product datasheet Reserved
* MUL: PLL Multiplier 0 = The PLL is deactivated. 1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1. * USBDIV: Divider for USB Clock
USBDIV 0 0 1 1 0 1 0 1 Divider for USB Clock(s) Divider output is PLL clock output. Divider output is PLL clock output divided by 2. Divider output is PLL clock output divided by 4. Reserved.
194
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26.9.10 PMC Master Clock Register PMC_MCKR Read/Write
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2 1
-
0
-
-
-
PRES
CSS
* CSS: Master Clock Selection
CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected Reserved PLL Clock is selected.
* PRES: Master Clock Prescaler
PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved
195
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26.9.11 PMC Programmable Clock Register PMC_PCKx Read/Write
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
PRES
CSS
* CSS: Master Clock Selection
CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected Reserved PLL Clock is selected
* PRES: Programmable Clock Prescaler
PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved
196
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26.9.12 PMC Interrupt Enable Register PMC_IER Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCKRDY3
3
PCKRDY2
2
PCKRDY1
1
PCKRDY0
0
-
-
-
-
MCKRDY
LOCK
-
MOSCS
* MOSCS: Main Oscillator Status Interrupt Enable * LOCK: PLL Lock Interrupt Enable * MCKRDY: Master Clock Ready Interrupt Enable * PCKRDYx: Programmable Clock Ready x Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
197
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26.9.13 PMC Interrupt Disable Register PMC_IDR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCKRDY3
3
PCKRDY2
2
PCKRDY1
1
PCKRDY0
0
-
-
-
-
MCKRDY
LOCK
-
MOSCS
* MOSCS: Main Oscillator Status Interrupt Disable * LOCK: PLL Lock Interrupt Disable * MCKRDY: Master Clock Ready Interrupt Disable * PCKRDYx: Programmable Clock Ready x Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
198
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26.9.14 PMC Status Register PMC_SR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCKRDY3
3
PCKRDY2
2
PCKRDY1
1
PCKRDY0
0
-
-
-
-
MCKRDY
LOCK
-
MOSCS
* MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. * LOCK: PLL Lock Status 0 = PLL is not locked 1 = PLL is locked. * MCKRDY: Master Clock Status 0 = Master Clock is not ready. 1 = Master Clock is ready. * PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready. 1 = Programmable Clock x is ready.
199
6120A-ATARM-01-Sep-05
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26.9.15 PMC Interrupt Mask Register PMC_IMR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCKRDY3
3
PCKRDY2
2
PCKRDY1
1
PCKRDY0
0
-
-
-
-
MCKRDY
LOCK
-
MOSCS
* MOSCS: Main Oscillator Status Interrupt Mask * LOCK: PLL Lock Interrupt Mask * MCKRDY: Master Clock Ready Interrupt Mask * PCKRDYx: Programmable Clock Ready x Interrupt Mask 0 = The corresponding interrupt is enabled. 1 = The corresponding interrupt is disabled.
200
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27. Debug Unit (DBGU)
27.1 Overview
The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel's ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. Moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control. Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM.
201
6120A-ATARM-01-Sep-05
27.2
Block Diagram
Figure 27-1. Debug Unit Functional Block Diagram
Peripheral Bridge Peripheral DMA Controller
APB
Debug Unit
DTXD
Transmit Power Management Controller
MCK
Baud Rate Generator Receive
Parallel Input/ Output
DRXD
COMMRX ARM Processor
nTRST
COMMTX
DCC Handler
Chip ID
ICE Access Handler
Interrupt Control
dbgu_irq
ice_nreset
force_ntrst
Table 27-1.
Pin Name DRXD DTXD
Debug Unit Pin Description
Description Debug Receive Data Debug Transmit Data Type Input Output
Figure 27-2. Debug Unit Application Example
Boot Program Debug Monitor Trace Manager
Debug Unit
RS232 Drivers Programming Tool Debug Console Trace Console
202
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27.3
27.3.1
Product Dependencies
I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
27.3.2
Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1.
27.3.3
Interrupt Source Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 27-1. This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered.
203
6120A-ATARM-01-Sep-05
27.4
UART Operations
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity). It has no clock pin. The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART.
27.4.1
Baud Rate Generator The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536). MCK Baud Rate = --------------------16 x CD
Figure 27-3. Baud Rate Generator
CD CD MCK 16-bit Counter
OUT
>1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock
27.4.2 27.4.2.1
Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost.
204
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27.4.2.2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. Figure 27-4. Start Bit Detection
Sampling Clock
DRXD
True Start Detection Baud Rate Clock
D0
Figure 27-5. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit period 1 bit period
DRXD
Sampling
D0 D1 True Start Detection
D2
D3
D4
D5
D6
D7 Parity Bit
Stop Bit
27.4.2.3
Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 27-6. Receiver Ready
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P
RXRDY
Read DBGU_RHR
205
6120A-ATARM-01-Sep-05
27.4.2.4
Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 27-7. Receiver Overrun
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY OVRE
RSTSTA
27.4.2.5
Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 27-8. Parity Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY PARE
Wrong Parity Bit
RSTSTA
27.4.2.6
Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 27-9. Receiver Framing Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY FRAME
Stop Bit Detected at 0
RSTSTA
206
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27.4.3 27.4.3.1 Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. 27.4.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 27-10. Character Transmission
Example: Parity enabled Baud Rate Clock DTXD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
27.4.3.3
Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed.
207
6120A-ATARM-01-Sep-05
Figure 27-11. Transmitter Control
DBGU_THR
Data 0 Data 1
Shift Register
Data 0
Data 1
DTXD
S
Data 0
P
stop
S
Data 1
P
stop
TXRDY TXEMPTY
Write Data 0 in DBGU_THR
Write Data 1 in DBGU_THR
27.4.4
Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR.
27.4.5
Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.
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Figure 27-12. Test Modes
Automatic Echo Receiver RXD
Transmitter
Disabled
TXD
Local Loopback Receiver
Disabled
RXD
VDD Transmitter
Disabled
TXD
Remote Loopback Receiver
VDD Disabled RXD
Transmitter
Disabled
TXD
27.4.6
Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel:
MRC p14, 0, Rd, c1, c0, 0
Returns the debug communication data read register into Rd
MCR p14, 0, Rd, c1, c0, 0
Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger.
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27.4.7
Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: * EXT - shows the use of the extension identifier register * NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size * ARCH - identifies the set of embedded peripheral * SRAMSIZ - indicates the size of the embedded SRAM * EPROC - indicates the embedded ARM processor * VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0.
27.4.8
ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.
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27.5 Debug Unit User Interface
Debug Unit Memory Map
Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Force NTRST Register Reserved PDC Area Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR - DBGU_CIDR DBGU_EXID DBGU_FNR - - Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write - Read-only Read-only Read/Write - - Reset Value - 0x0 - - 0x0 - 0x0 - 0x0 - - - 0x0 - -
Table 27-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020
0x0024 - 0x003C 0x0040 0x0044 0x0048 0x004C - 0x00FC 0x0100 - 0x0124
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27.5.1 Name:
Debug Unit Control Register DBGU_CR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8 RSTSTA 0
-
7 TXDIS
-
6 TXEN
-
5 RXDIS
-
4 RXEN
-
3 RSTTX
-
2 RSTRX
-
1
-
-
* RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. * RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. * RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. * RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. * TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. * TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. * RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.
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27.5.2 Name: Access Type:
31
Debug Unit Mode Register DBGU_MR Read/Write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15 CHMODE 7
-
14
-
13
-
12
-
11
-
10 PAR
-
9
-
8
-
6 5
-
4 3
-
1 0
2
-
-
-
-
-
-
-
-
* PAR: Parity Type
PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity
* CHMODE: Channel Mode
CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback
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27.5.3 Name:
Debug Unit Interrupt Enable Register DBGU_IER Write-only
30 COMMTX 22 29 28 27 26 25 24
Access Type:
31 COMMRX 23
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 RXBUFF 4 ENDTX
-
11 TXBUFE 3 ENDRX
-
10
-
9 TXEMPTY 1 TXRDY
-
8
-
7 PARE
-
6 FRAME
-
5 OVRE
-
2
-
0 RXRDY
-
* RXRDY: Enable RXRDY Interrupt * TXRDY: Enable TXRDY Interrupt * ENDRX: Enable End of Receive Transfer Interrupt * ENDTX: Enable End of Transmit Interrupt * OVRE: Enable Overrun Error Interrupt * FRAME: Enable Framing Error Interrupt * PARE: Enable Parity Error Interrupt * TXEMPTY: Enable TXEMPTY Interrupt * TXBUFE: Enable Buffer Empty Interrupt * RXBUFF: Enable Buffer Full Interrupt * COMMTX: Enable COMMTX (from ARM) Interrupt * COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt.
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27.5.4 Name: Access Type:
31 COMMRX 23
Debug Unit Interrupt Disable Register DBGU_IDR Write-only
30 COMMTX 22 29 28 27 26 25 24
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 RXBUFF 4 ENDTX
-
11 TXBUFE 3 ENDRX
-
10
-
9 TXEMPTY 1 TXRDY
-
8
-
7 PARE
-
6 FRAME
-
5 OVRE
-
2
-
0 RXRDY
-
* RXRDY: Disable RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Disable End of Receive Transfer Interrupt * ENDTX: Disable End of Transmit Interrupt * OVRE: Disable Overrun Error Interrupt * FRAME: Disable Framing Error Interrupt * PARE: Disable Parity Error Interrupt * TXEMPTY: Disable TXEMPTY Interrupt * TXBUFE: Disable Buffer Empty Interrupt * RXBUFF: Disable Buffer Full Interrupt * COMMTX: Disable COMMTX (from ARM) Interrupt * COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt.
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27.5.5 Name:
Debug Unit Interrupt Mask Register DBGU_IMR Read-only
30 COMMTX 22 29 28 27 26 25 24
Access Type:
31 COMMRX 23
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 RXBUFF 4 ENDTX
-
11 TXBUFE 3 ENDRX
-
10
-
9 TXEMPTY 1 TXRDY
-
8
-
7 PARE
-
6 FRAME
-
5 OVRE
-
2
-
0 RXRDY
-
* RXRDY: Mask RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Mask End of Receive Transfer Interrupt * ENDTX: Mask End of Transmit Interrupt * OVRE: Mask Overrun Error Interrupt * FRAME: Mask Framing Error Interrupt * PARE: Mask Parity Error Interrupt * TXEMPTY: Mask TXEMPTY Interrupt * TXBUFE: Mask TXBUFE Interrupt * RXBUFF: Mask RXBUFF Interrupt * COMMTX: Mask COMMTX Interrupt * COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
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27.5.6 Name: Access Type:
31 COMMRX 23
Debug Unit Status Register DBGU_SR Read-only
30 COMMTX 22 29 28 27 26 25 24
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 RXBUFF 4 ENDTX
-
11 TXBUFE 3 ENDRX
-
10
-
9 TXEMPTY 1 TXRDY
-
8
-
7 PARE
-
6 FRAME
-
5 OVRE
-
2
-
0 RXRDY
-
* RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. * TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. * ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active. * ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. * OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. * FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. * PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. * TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. * TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active.
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* RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. * COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. * COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active.
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27.5.7 Name: Access Type:
31
Debug Unit Receiver Holding Register DBGU_RHR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4 RXCHR
-
3
-
2
-
1
-
0
* RXCHR: Received Character Last received character if RXRDY is set.
27.5.8 Name:
Debug Unit Transmit Holding Register DBGU_THR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4 TXCHR
-
3
-
2
-
1
-
0
* TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
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27.5.9 Name:
Debug Unit Baud Rate Generator Register DBGU_BRGR Read/Write
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 CD
-
11
-
10
-
9
-
8
7
6
5
4 CD
3
2
1
0
* CD: Clock Divisor
CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16)
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27.5.10 Name: Access Type:
31 EXT 23 22 ARCH 15 14 NVPSIZ2 7 6 EPROC 5 4 3 2 VERSION 13 12 11 10 NVPSIZ 1 0
Debug Unit Chip ID Register DBGU_CIDR Read-only
30 29 NVPTYP 21 20 19 18 SRAMSIZ 9 8 28 27 26 ARCH 17 16 25 24
* VERSION: Version of the Device * EPROC: Embedded Processor
EPROC 0 0 1 1 0 1 0 0 1 0 0 1 Processor ARM946ES ARM7TDMI ARM920T ARM926EJS
* NVPSIZ: Nonvolatile Program Memory Size
NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved
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* NVPSIZ2 Second Nonvolatile Program Memory Size
NVPSIZ2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved
* SRAMSIZ: Internal SRAM Size
SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes Reserved 112K bytes 4K bytes 80K bytes 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 128K bytes 256K bytes 96K bytes 512K bytes
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* ARCH: Architecture Identifier
ARCH Hex 0xF0 0x40 0x63 0x55 0x42 0x92 0x34 0x60 0x70 0x71 0x72 0x73 0x19 Bin 1111 0001 0100 0000 0110 0011 0101 0101 0100 0010 1001 0010 0011 0100 0101 0000 0111 0000 0111 0001 0111 0010 0111 0011 0001 1001 Architecture AT75Cxx Series AT91x40 Series AT91x63 Series AT91x55 Series AT91x42 Series AT91x92 Series AT91x34 Series AT91SAM7Axx Series AT91SAM7Sxx Series AT91SAMXxx Series AT91SAM7SExx Series AT91SAM7Lxx Series AT91SAM9xx Series
* NVPTYP: Nonvolatile Program Memory Type
NVPTYP 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 Memory ROM ROMless or on-chip Flash SRAM emulating ROM Embedded Flash Memory ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size
* EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists.
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27.5.11 Name:
Debug Unit Chip ID Extension Register DBGU_EXID Read-only
30 29 28 EXID 27 26 25 24
Access Type:
31
23
22
21
20 EXID
19
18
17
16
15
14
13
12 EXID
11
10
9
8
7
6
5
4 EXID
3
2
1
0
* EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
27.5.12 Name:
Debug Unit Force NTRST Register DBGU_FNR Read/Write
30 29 28 27 26 25 24
Access T ype:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0 FNTRST
-
-
-
-
-
-
-
* FNTRST: Force NTRST 0 = NTRST of the ARM processor's TAP controller is driven by the ice_nreset signal. 1 = NTRST of the ARM processor's TAP controller is held low.
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28. Parallel Input/Output Controller (PIO)
28.1 Overview
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: * An input change interrupt enabling level change detection on any I/O line. * A glitch filter providing rejection of pulses lower than one-half of clock cycle. * Multi-drive capability similar to an open drain I/O line. * Control of the the pull-up of the I/O line. * Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
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28.2
Block Diagram
Figure 28-1. Block Diagram
PIO Controller
AIC PIO Interrupt
PMC
PIO Clock
Data, Enable
Embedded Peripheral
Up to 32 peripheral IOs
PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31
APB
28.3
Application Block Diagram
Figure 28-2. Application Block Diagram
On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals
PIO Controller
Keyboard Driver General Purpose I/Os External Devices
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28.4
28.4.1
Product Dependencies
Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.
28.4.2
External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs.
28.4.3
Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information.
28.4.4
Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.
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28.5
Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 28-3. In this description each signal shown represents but one of up to 32 possible indexes.
Figure 28-3. I/O Line Control Logic
PIO_OER[0] PIO_OSR[0] PIO_ODR[0]
1
PIO_PUER[0] PIO_PUSR[0] PIO_PUDR[0]
Peripheral A Output Enable Peripheral B Output Enable PIO_ASR[0] PIO_ABSR[0] PIO_BSR[0] Peripheral A Output Peripheral B Output
0
0 0
1 PIO_PER[0] PIO_PSR[0] PIO_PDR[0] 0
0
1
PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 1
1
1
PIO_SODR[0] PIO_ODSR[0] PIO_CODR[0]
Pad 0
Peripheral A Input Peripheral B Input
PIO_PDSR[0] 0 Edge Detector Glitch Filter PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] 1
PIO_ISR[0]
(Up to 32 possible inputs) PIO Interrupt
PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31]
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28.5.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The value of this resistor is about 10 k (see the product electrical characteristics for more details about this value). The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. 28.5.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. 28.5.3 Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. 28.5.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not.
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When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 28.5.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OSWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 28.5.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 28.5.7 Output Line Timings Figure 28-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 28-4 also shows when the feedback in PIO_PDSR is available.
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Figure 28-4. Output Line Timings
MCK
Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0
APB Access
APB Access
PIO_ODSR 2 cycles PIO_PDSR 2 cycles
28.5.8
Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
28.5.9
Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 28-5. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled.
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Figure 28-5. Input Glitch Filter Timing
MCK up to 1.5 cycles Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 up to 2.5 cycles 1 cycle up to 2 cycles 1 cycle 1 cycle 1 cycle
28.5.10
Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled.
Figure 28-6. Input Change Interrupt Timings
MCK
Pin Level
PIO_ISR
Read PIO_ISR
APB Access
APB Access
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28.6 I/O Lines Programming Example
The programing example as shown in Table 28-1 below is used to define the following configuration. * 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor * Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor * Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts * Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter * I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor * I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor * I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 28-1. Programming Example
Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0
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28.7
Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically.
Table 28-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C
Parallel Input/Output Controller (PIO) Register Mapping
Register PIO Enable Register PIO Disable Register PIO Status Register (1) Reserved Output Enable Register Output Disable Register Output Status Register Reserved Glitch Input Filter Enable Register Glitch Input Filter Disable Register Glitch Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register Pin Data Status Register
(3) (2)
Name PIO_PER PIO_PDR PIO_PSR
Access Write-only Write-only Read-only
Reset Value - - 0x0000 0000
PIO_OER PIO_ODR PIO_OSR
Write-only Write-only Read-only
- - 0x0000 0000
PIO_IFER PIO_IFDR PIO_IFSR
Write-only Write-only Read-only
- - 0x0000 0000
PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR
Write-only Write-only Read-only Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only
- - 0x0000 0000
Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register
(4)
- - 0x00000000 0x00000000 - - 0x00000000
PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR
Multi-driver Enable Register Multi-driver Disable Register Multi-driver Status Register Reserved Pull-up Disable Register Pull-up Enable Register Pad Pull-up Status Register Reserved
PIO_PUDR PIO_PUER PIO_PUSR
Write-only Write-only Read-only
- - 0x00000000
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Table 28-2.
Offset 0x0070 0x0074 0x0078 0x007C - 0x009C 0x00A0 0x00A4 0x00A8
Parallel Input/Output Controller (PIO) Register Mapping (Continued)
Register Peripheral A Select Register(5) Peripheral B Select Register AB Status Register Reserved Output Write Enable Output Write Disable Output Write Status Register PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only - - 0x00000000
(5) (5)
Name PIO_ASR PIO_BSR PIO_ABSR
Access Write-only Write-only Read-only
Reset Value - - 0x00000000
0x00AC - 0x00FC Reserved Notes: 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register.
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6120A-ATARM-01-Sep-05
28.7.1 Name:
PIO Controller PIO Enable Register PIO_PER Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
28.7.2 Name:
PIO Controller PIO Disable Register PIO_PDR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
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28.7.3 Name: Access Type:
31
PIO Controller PIO Status Register PIO_PSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive).
28.7.4 Name:
PIO Controller Output Enable Register PIO_OER Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line.
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28.7.5 Name:
PIO Controller Output Disable Register PIO_ODR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line.
28.7.6 Name:
PIO Controller Output Status Register PIO_OSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output.
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28.7.7 Name: Access Type:
31
PIO Controller Input Filter Enable Register PIO_IFER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line.
28.7.8 Name:
PIO Controller Input Filter Disable Register PIO_IFDR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line.
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28.7.9 Name:
PIO Controller Input Filter Status Register PIO_IFSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line.
28.7.10 Name:
PIO Controller Set Output Data Register PIO_SODR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line.
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28.7.11 Name: Access Type:
31
PIO Controller Clear Output Data Register PIO_CODR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line.
28.7.12 Name:
PIO Controller Output Data Status Register PIO_ODSR Read-only or Read/Write
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1.
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28.7.13 Name:
PIO Controller Pin Data Status Register PIO_PDSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1.
28.7.14 Name:
PIO Controller Interrupt Enable Register PIO_IER Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line.
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28.7.15 Name: Access Type:
31
PIO Controller Interrupt Disable Register PIO_IDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line.
28.7.16 Name:
PIO Controller Interrupt Mask Register PIO_IMR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line.
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28.7.17 Name:
PIO Controller Interrupt Status Register PIO_ISR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
28.7.18 Name:
PIO Multi-driver Enable Register PIO_MDER Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line.
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28.7.19 Name: Access Type:
31
PIO Multi-driver Disable Register PIO_MDDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line.
28.7.20 Name:
PIO Multi-driver Status Register PIO_MDSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
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28.7.21 Name:
PIO Pull Up Disable Register PIO_PUDR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line.
28.7.22 Name:
PIO Pull Up Enable Register PIO_PUER Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line.
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28.7.23 Name: Access Type:
31
PIO Pull Up Status Register PIO_PUSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line.
28.7.24 Name:
PIO Peripheral A Select Register PIO_ASR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function.
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28.7.25 Name:
PIO Peripheral B Select Register PIO_BSR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function.
28.7.26 Name:
PIO Peripheral A B Status Register PIO_ABSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B.
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28.7.27 Name: Access Type:
31
PIO Output Write Enable Register PIO_OWER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line.
28.7.28 Name:
PIO Output Write Disable Register PIO_OWDR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line.
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28.7.29 Name:
PIO Output Write Status Register PIO_OWSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line.
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29. Serial Peripheral Interface (SPI)
29.1 Overview
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the "master"' which controls the data flow, while the other devices act as "slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: * Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). * Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. * Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. * Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
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6120A-ATARM-01-Sep-05
29.2
Block Diagram
Figure 29-1. Block Diagram
PDC APB SPCK MISO MCK SPI Interface DIV PIO MOSI NPCS0/NSS NPCS1 NPCS2 MCK(1) N Interrupt Control NPCS3
PMC
SPI Interrupt
Note:
1. N = 32
29.3
Application Block Diagram
Figure 29-2. Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS
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29.4 Signal Description
Table 29-1.
Signal Description
Type
Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS
Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select
Master Input Output Output Output Output
Slave Output Input Input Unused Input
29.5
29.5.1
Product Dependencies
I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions.
29.5.2
Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock.
29.5.3
Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI.
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29.6
29.6.1
Functional Description
Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.
29.6.2
Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 29-2 shows the four modes and corresponding parameter settings. Table 29-2. SPI Bus Protocol Mode
SPI Mode 0 1 2 3 CPOL 0 0 1 1 NCPHA 1 0 1 0
Figure 29-3 and Figure 29-4 show examples of data transfers.
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Figure 29-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8
SPCK (CPOL = 1)
MOSI (from master)
MSB
6
5
4
3
2
1
LSB
MISO (from slave)
MSB
6
5
4
3
2
1
LSB
*
NSS (to slave)
* Not defined, but normally MSB of previous character received.
Figure 29-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8
SPCK (CPOL = 1)
MOSI (from master)
MSB
6
5
4
3
2
1
LSB
MISO (from slave)
*
MSB
6
5
4
3
2
1
LSB
NSS (to slave)
* Not defined but normally LSB of previous character transmitted.
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6120A-ATARM-01-Sep-05
29.6.3
Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. No transfer is started when writing into the SPI_TDR if the PCS field does not select a slave. The PCS field is set by writing the SPI_TDR in variable mode, or the SPI_MR in fixed mode, depending on the value of PCS field. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, no data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 29-5 on page 257 shows a block diagram of the SPI when operating in Master Mode. Figure 29-6 on page 258 shows a flow chart describing how transfers are handled.
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29.6.3.1 Master Mode Block Diagram Figure 29-5. Master Mode Block Diagram
FDIV MCK
SPI_CSR0..3 SCBR 0 Baud Rate Generator SPCK
MCK/N
1 SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB
SPI_RDR RD
RDRF OVRES
MISO
Shift Register
MSB
MOSI
SPI_TDR TD SPI_CSR0..3 CSAAT PS SPI_MR PCS 0 SPI_TDR PCS 1 NPCS0 PCSDEC Current Peripheral SPI_RDR PCS NPCS3 NPCS2 NPCS1 TDRE
MSTR NPCS0 MODFDIS
MODF
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29.6.3.2
Master Mode Flow Diagram
Figure 29-6. Master Mode Flow Diagram S
SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ?
0 1 CSAAT ? PS ? Variable peripheral yes 0 Fixed peripheral
0 0 PS ? Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral
1
SPI_TDR(PCS) = NPCS ? no NPCS = 0xF
SPI_MR(PCS) = NPCS ? no NPCS = 0xF
1
NPCS = SPI_TDR(PCS)
Delay DLYBCS
Delay DLYBCS
NPCS = SPI_TDR(PCS)
NPCS = SPI_MR(PCS), SPI_TDR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD) TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer RDRF = 1
Delay DLYBCT
0 TDRE ?
1
1 CSAAT ?
0 NPCS = 0xF
Delay DLYBCS
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29.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock divided by 32, by a value between 2 and 255. The selection between Master Clock or Master Clock divided by N is done by the FDIV value set in the Mode Register This allows a maximum operating baud rate at up to Master Clock/2 and a minimum operating baud rate of MCK divided by 255*32. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 29.6.3.4 Transfer Delays Figure 29-7 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: * The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. * The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. * The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 29-7. Programmable Delays
Chip Select 1
Chip Select 2
SPCK DLYBCS DLYBS DLYBCT DLYBCT
29.6.3.5
Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: 259
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* Fixed Peripheral Select: SPI exchanges data with only one peripheral * Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS fields of the Chip Select Registers have no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 29.6.3.6 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 29.6.3.7 Peripheral Deselection When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers.
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To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. Figure 29-8 shows different peripheral deselection cases and the effect of the CSAAT bit. Figure 29-8. Peripheral Deselection
CSAAT = 0 CSAAT = 1
TDRE
DLYBCT A DLYBCS PCS = A A A
DLYBCT A DLYBCS PCS = A A
NPCS[0..3]
Write SPI_TDR
TDRE
DLYBCT A DLYBCS PCS=A A A
DLYBCT A DLYBCS PCS = A A
NPCS[0..3]
Write SPI_TDR
TDRE NPCS[0..3]
DLYBCT A DLYBCS PCS = B B A
DLYBCT B DLYBCS PCS = B
Write SPI_TDR
29.6.3.8
Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. As this pin is generally configured in opendrain, it is important that a pull up resistor is connected on the NPCS0 line, so that a high level is guaranteed and no spurious mode fault is detected. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
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29.6.4
SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If RDRF is already high when the data is transferred, the Overrun bit rises and the data transfer to SPI_RDR is aborted. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 29-9 shows a block diagram of the SPI when operating in Slave Mode. Figure 29-9. Slave Mode Functional Block Diagram
SPCK NSS SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RD RDRF OVRES SPI Clock
Shift Register
MSB
MISO
SPI_TDR FLOAD TD TDRE
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29.7 Serial Peripheral Interface (SPI) User Interface
Serial Peripheral Interface (SPI) Register Mapping
Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 - Read/Write Read/Write Read/Write Read/Write - 0x0 0x0 0x0 0x0 - Register Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0
Table 29-3.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C
0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x004C - 0x00FC 0x100 - 0x124
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29.7.1 Name:
SPI Control Register SPI_CR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
LASTXFER
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
SWRST
-
-
-
-
-
SPIDIS
SPIEN
* SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. * SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. * SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. * LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.
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29.7.2 Name: Access Type:
31
SPI Mode Register SPI_MR Read/Write
30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
LLB
-
-
MODFDIS
FDIV
PCSDEC
PS
MSTR
* MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. * PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. * PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 15. * FDIV: Clock Selection 0 = The SPI operates at MCK. 1 = The SPI operates at MCK/N. * MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. * LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in Master Mode only. * PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0).
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If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. * DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods (or 6*N MCK periods if FDIV is set) will be inserted by default. Otherwise, the following equation determines the delay: If FDIV is 0: DLYBCS Delay Between Chip Selects = ---------------------MCK If FDIV is 1: DLYBCS x N Delay Between Chip Selects = --------------------------------MCK NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected)
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29.7.3 Name: Access Type:
31
SPI Receive Data Register SPI_RDR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
RD
7 6 5 4 3 2 1 0
RD
* RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. * PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.
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29.7.4 Name:
SPI Transmit Data Register SPI_TDR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
LASTXFER
16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
TD
7 6 5 4 3 2 1 0
TD
* TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS * LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected)
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29.7.5 Name: Access Type:
31
SPI Status Register SPI_SR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
SPIENS
8
-
7
-
6
-
5
-
4
-
3
-
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. * TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. * MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. * OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. * ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR or SPI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR or SPI_RNCR. * ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR or SPI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR or SPI_TNCR. * RXBUFF: RX Buffer Full 0 = SPI_RCR or SPI_RNCR has a value other than 0. 1 = Both SPI_RCR and SPI_RNCR has a value of 0.
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* TXBUFE: TX Buffer Empty 0 = SPI_TCR or SPI_TNCR has a value other than 0. 1 = Both SPI_TCR and SPI_TNCR has a value of 0. * NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. * TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. * SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled.
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29.7.6 Name: Access Type:
31
SPI Interrupt Enable Register SPI_IER Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Enable * TDRE: SPI Transmit Data Register Empty Interrupt Enable * MODF: Mode Fault Error Interrupt Enable * OVRES: Overrun Error Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable * TXEMPTY: Transmission Registers Empty Enable * NSSR: NSS Rising Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
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29.7.7 Name:
SPI Interrupt Disable Register SPI_IDR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Disable * TDRE: SPI Transmit Data Register Empty Interrupt Disable * MODF: Mode Fault Error Interrupt Disable * OVRES: Overrun Error Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable * TXEMPTY: Transmission Registers Empty Disable * NSSR: NSS Rising Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
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29.7.8 Name: Access Type:
31
SPI Interrupt Mask Register SPI_IMR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Mask * TDRE: SPI Transmit Data Register Empty Interrupt Mask * MODF: Mode Fault Error Interrupt Mask * OVRES: Overrun Error Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask * TXEMPTY: Transmission Registers Empty Mask * NSSR: NSS Rising Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
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29.7.9 Name:
SPI Chip Select Register SPI_CSR0... SPI_CSR3 Read/Write
30 29 28 27 26 25 24
Access Type:
31
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS
CSAAT
-
NCPHA
CPOL
* CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. * NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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* SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: If FDIV is 0: MCK SPCK Baudrate = -------------SCBR If FDIV is 1: MCK SPCK Baudrate = -----------------------------( N x SCBR )
Note:
N = 32
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. * DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: If FDIV is 0: DLYBS Delay Before SPCK = -----------------MCK If FDIV is 1: Delay Before SPCK = N x DLYBS ----------------------------MCK
Note:
N = 32
* DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay:
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If FDIV is 0: 32 x DLYBCT SCBR Delay Between Consecutive Transfers = ------------------------------------ + ---------------MCK 2MCK If FDIV is 1: 32 x N x DLYBCT N x SCBR Delay Between Consecutive Transfers = ------------------------------------------------ + ------------------------MCK 2MCK
Note:
N = 32
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30. Two-wire Interface (TWI)
30.1 Overview
The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel two-wire bus Serial EEPROM. The TWI is programmable as a master with sequential or single-byte access. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.
30.2
Block Diagram
Figure 30-1. Block Diagram
APB Bridge
TWCK PIO Two-wire Interface TWD
PMC
MCK
TWI Interrupt
AIC
30.3
Application Block Diagram
Figure 30-2. Application Block Diagram
VDD R TWD TWCK R
Host with TWI Interface
AT24LC16 U1 Slave 1
AT24LC16 U2 Slave 2
LCD Controller U3 Slave 3
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30.4
30.4.1
Product Dependencies
I/O Lines Description
Table 30-1.
Pin Name TWD TWCK
I/O Lines Description
Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output
Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 30-2 on page 277). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: * Program the PIO controller to: - Dedicate TWD and TWCK as peripheral lines. - Define TWD and TWCK as open-drain. 30.4.2 Power Management * Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 30.4.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI.
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30.5
30.5.1
Functional Description
Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 30-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 30-3). * A high-to-low transition on the TWD line while TWCK is high defines the START condition. * A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 30-3. START and STOP Conditions
TWD
TWCK Start Stop
Figure 30-4. Transfer Format
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
30.5.2
Modes of Operation The TWI has two modes of operation: * Master transmitter mode * Master receiver mode The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks.
30.5.3
Transmitting Data After the master initiates a Start condition, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write operation (transmit operation). If the bit is 1, it indicates a request for data read (receive operation). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and
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sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in the control register starts the transmission. The data is shifted in the internal shifter and when an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Figure 306 below). The master generates a stop condition to end the transfer. The read sequence begins by setting the START bit. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address). The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). Figure 30-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P
Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A DATA A P
One byte internal address TWD S DADR W A IADR(7:0) A DATA A P
Figure 30-6. Master Write with One Byte Internal Address and Multiple Data Bytes
TWD S DADR W A IADR(7:0) A DATA A DATA A DATA A P
TXCOMP Write THR TXRDY Write THR Write THR Write THR
Figure 30-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A S DADR R A
DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A S DADR R A DATA
N
P
N
P
One byte internal address TWD S DADR W A IADR(7:0) A S DADR R A DATA N P
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Figure 30-8. Master Read with One Byte Internal Address and Multiple Data Bytes
TWD S DADR W A IADR(7:0) A S DADR R A DATA A DATA N P
TXCOMP Write START Bit RXRDY Write STOP Bit
Read RHR
Read RHR
* S = Start * P = Stop * W = Write * R = Read * A = Acknowledge * N = Not Acknowledge * DADR = Device Address * IADR = Internal Address Figure 30-9 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 30-9. Internal Address Usage
S T A R T W R I T E S T O P
Device Address 0 M S B
FIRST WORD ADDRESS
SECOND WORD ADDRESS
DATA
LRA S/C BW K
M S B
A C K
LA SC BK
A C K
30.5.4
Read/Write Flowcharts The following flowcharts shown in Figure 30-10 on page 282 and in Figure 30-11 on page 283 give examples for read and write operations in Master Mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
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Figure 30-10. TWI Write in Master Mode
START
Set TWI clock: TWI_CWGR = clock
Set the control register: - Master enable TWI_CR = MSEN
Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Write ==> bit MREAD = 0
Internal address size = 0? Set theinternal address TWI_IADR = address
Yes Load transmit register TWI_THR = Data to send Start the transfer TWI_CR = START
Read status register
TWI_THR = data to send TXRDY = 0? Yes
Data to send? Yes
Stop the transfer TWI_CR = STOP
Read status register
TXCOMP = 0?
Yes
END
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Figure 30-11. TWI Read in Master Mode
START
Set TWI clock: TWI_CWGR = clock
Set the control register: - Master enable - Slave disable TWI_CR = MSEN
Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Read ==> bit MREAD = 0
Internal address size = 0? Set the internal address TWI_IADR = address
Yes Start the transfer TWI_CR = START
Read status register
RXRDY = 0?
Yes
Data to read? Yes
Stop the transfer TWI_CR = STOP
Read status register
TXCOMP = 0?
Yes
END
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30.6
Two-wire Interface (TWI) User Interface
Two-wire Interface (TWI) Register Mapping
Register Control Register Master Mode Register Reserved Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Name TWI_CR TWI_MMR - TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR - Access Write-only Read/Write - Read/Write Read/Write Read-only Write-only Write-only Read-only Read-only Read/Write - Reset Value N/A 0x0000 - 0x0000 0x0000 0x0008 N/A N/A 0x0000 0x0000 0x0000 -
Table 30-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034
0x0038-0x00FC
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30.6.1 TWI Control Register TWI_CR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 MSDIS 26 - 18 - 10 - 2 MSEN 25 - 17 - 9 - 1 STOP 24 - 16 - 8 - 0 START
Register Name: Access Type:
31 - 23 - 15 - 7 SWRST
* START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. * STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read or write mode. In single data byte master read or write, the START and STOP must both be set. In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission. In master read mode, if a NACK bit is received, the STOP is automatically performed. In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. * MSEN: TWI Master Transfer Enabled 0 = No effect. 1 = If MSDIS = 0, the master data transfer is enabled. * MSDIS: TWI Master Transfer Disabled 0 = No effect. 1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. * SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.
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30.6.2
TWI Master Mode Register TWI_MMR Read/Write
30 - 22 29 - 21 28 - 20 27 - 19 DADR 11 - 3 - 26 - 18 25 - 17 24 - 16
Register Name: Address Type:
31 - 23 - 15 - 7 -
14 - 6 -
13 - 5 -
12 MREAD 4 -
10 - 2 -
9 IADRSZ 1 -
8
0 -
* IADRSZ: Internal Device Address Size
IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address (Byte command protocol) One-byte internal device address Two-byte internal device address Three-byte internal device address
* MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. * DADR: Device Address The device address is used in Master Mode to access slave devices in read or write mode.
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30.6.3 TWI Internal Address Register TWI_IADR Read/Write
30 - 22 29 - 21 28 - 20 IADR 15 14 13 12 IADR 7 6 5 4 IADR 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 - 16
Register Name: Access Type:
31 - 23
* IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. - Low significant byte address in 10-bit mode addresses. 30.6.4 TWI Clock Waveform Generator Register TWI_CWGR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CHDIV 7 6 5 4 CLDIV 3 2 1 0 27 - 19 - 11 26 - 18 25 - 17 CKDIV 9 24 - 16
Register Name: Access Type:
31 - 23 - 15
10
8
* CLDIV: Clock Low Divider The SCL low period is defined as follows:
T low = ( ( CLDIV x 2
CKDIV
) + 3 ) x T MCK
* CHDIV: Clock High Divider The SCL high period is defined as follows:
T high = ( ( CHDIV x 2
CKDIV
) + 3 ) x T MCK
* CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods.
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30.6.5
TWI Status Register TWI_SR Read-only
30 - 22 - 14 - 6 OVRE 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP
Register Name: Access Type:
31 - 23 - 15 - 7 UNRE
* TXCOMP: Transmission Completed 0 = In master, during the length of the current frame. In slave, from START received to STOP received. 1 = When both holding and shift registers are empty and STOP condition has been sent (in Master) or when MSEN is set (enable TWI). * RXRDY: Receive Holding Register Ready 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. * TXRDY: Transmit Holding Register Ready 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). * OVRE: Overrun Error 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. * UNRE: Underrun Error 0 = No underrun error 1 = No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in Master Mode. Reset by read in TWI_SR when TXCOMP is set. * NACK: Not Acknowledged 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
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30.6.6 TWI Interrupt Enable Register TWI_IER Write-only
30 - 22 - 14 - 6 OVRE 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP
Register Name: Access Type:
31 - 23 - 15 - 7 UNRE
* TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * OVRE: Overrun Error * UNRE: Underrun Error * NACK: Not Acknowledge 0 = No effect. 1 = Enables the corresponding interrupt.
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30.6.7
TWI Interrupt Disable Register TWI_IDR Write-only
30 - 22 - 14 - 6 OVRE 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP
Register Name: Access Type:
31 - 23 - 15 - 7 UNRE
* TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * OVRE: Overrun Error * UNRE: Underrun Error * NACK: Not Acknowledge 0 = No effect. 1 = Disables the corresponding interrupt.
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30.6.8 TWI Interrupt Mask Register TWI_IMR Read-only
30 - 22 - 14 - 6 OVRE 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP
Register Name: Access Type:
31 - 23 - 15 - 7 UNRE
* TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * OVRE: Overrun Error * UNRE: Underrun Error * NACK: Not Acknowledge 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
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30.6.9
TWI Receive Holding Register TWI_RHR Read-only
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXDATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* RXDATA: Master or Slave Receive Holding Data
30.6.10
TWI Transmit Holding Register TWI_THR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXDATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* TXDATA: Master or Slave Transmit Holding Data
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31. Universal Synchronous Asynchronous Receiver Transmitter (USART)
31.1 Overview
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver timeout enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor.
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31.2
Block Diagram
Figure 31-1. USART Block Diagram
Peripheral DMA Controller Channel Channel
USART
PIO Controller
RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS DTR PMC MCK MCK/DIV Modem Signals Control DSR DCD RI SLCK Baud Rate Generator SCK
DIV
User Interface
APB
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31.3 Application Block Diagram
Figure 31-2. Application Block Diagram
PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver
USART
RS232 Drivers Modem PSTN
RS232 Drivers
RS485 Drivers
Smart Card Slot
IrDA Transceivers
Serial Port
Differential Bus
31.4
I/O Lines Description
I/O Line Description
Description Serial Clock Transmit Serial Data Receive Serial Data Ring Indicator Data Set Ready Data Carrier Detect Data Terminal Ready Clear to Send Request to Send Type I/O I/O Input Input Input Input Output Input Output Low Low Low Low Low Low Active Level
Table 31-1.
Name SCK TXD RXD RI DSR DCD DTR CTS RTS
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31.5
31.5.1
Product Dependencies
I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. All the pins of the modems may or may not be implemented on the USART within a product. Frequently, only the USART1 is fully equipped with all the modem signals. For the other USARTs of the product not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART.
31.5.2
Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled.
31.5.3
Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.
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31.6 Functional Description
The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: * 5- to 9-bit full-duplex asynchronous serial communication - MSB- or LSB-first - 1, 1.5 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling receiver frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication * High-speed 5- to 9-bit full-duplex synchronous serial communication - MSB- or LSB-first - 1 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling frequency - Optional hardware handshaking - Optional modem signals management - Optional break management - Optional multidrop serial communication * RS485 with driver control signal * ISO7816, T0 or T1 protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * InfraRed IrDA Modulation and Demodulation * Test modes - Remote loopback, local loopback, automatic echo 31.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: * the Master Clock MCK * a division of the Master Clock, the divider being product dependent, but generally set to 8 * the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive.
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If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 31-3. Baud Rate Generator
USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC
SCK
31.6.1.1
Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate.
SelectedClock Baudrate = -------------------------------------------( 8 ( 2 - Over )CD )
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. Baud Rate Calculation Example Table 31-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 31-2. Baud Rate Example (OVER = 0)
Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 6 8 8 12 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 0.00% 0.00% 1.70% 0.00% Error
Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800
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Table 31-2. Baud Rate Example (OVER = 0) (Continued)
Expected Baud Rate 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 Calculation Result 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 97.66 113.93 CD 13 20 20 23 24 30 39 40 40 52 53 54 65 81 98 114 Actual Baud Rate 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 38 265.31 38 377.19 Error 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% 0.35% 0.06%
Source Clock 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 60 000 000 70 000 000
The baud rate is calculated with the following formula: BaudRate = MCK CD x 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.
ExpectedBaudRate Error = 1 - -------------------------------------------------- ActualBaudRate
31.6.1.2
Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART functional mode. The fractional Baud Rate is calculated using the following formula:
SelectedClock Baudrate = --------------------------------------------------------------- 8 ( 2 - Over ) CD + FP ------ 8
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The modified architecture is presented below: Figure 31-4. Fractional Baud Rate Generator
FP
USCLKS MCK MCK/DIV SCK Reserved
CD
Modulus Control FP CD SCK FIDI 0 OVER Sampling Divider 1 1 SYNC USCLKS = 3 Sampling Clock 0 Baud Rate Clock SYNC
0 1 2 3 16-bit Counter glitch-free logic
>1 1
0
0
31.6.1.3
Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.
BaudRate = SelectedClock ------------------------------------CD
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 31.6.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula:
Di B = ----- x f Fi
where: * B is the bit rate * Di is the bit-rate adjustment factor * Fi is the clock frequency division factor * f is the ISO7816 clock frequency (Hz)
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Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 31-3. Table 31-3.
DI field Di (decimal)
Binary and Decimal Values for D
0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 31-4. Table 31-4.
FI field Fi (decimal
Binary and Decimal Values for F
0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048
Table 31-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 31-5.
Fi/Di 1 2 4 8 16 32 12 20
Possible Values for the Fi/Di Ratio
372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4
If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 31-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock.
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Figure 31-5. Elementary Time Unit (ETU)
FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD
1 ETU
31.6.2
Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The reset commands have the same effect as a hardware reset on the corresponding logic. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally.
31.6.3 31.6.3.1
Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only.
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Figure 31-6. Character Transmit
Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY raises. Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in US_THR while TXRDY is active has no effect and the written character is lost. Figure 31-7. Transmitter Status
Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Write US_THR TXRDY
TXEMPTY
31.6.3.2
Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 31-8 illustrates this coding scheme.
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Figure 31-8. NRZ to Manchester Encoding
NRZ encoded data Manchester encoded data 1 0 1 1 0 0 0 1
Txd
The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 31-9 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. Figure 31-9. Preamble Patterns, Default Polarity Assumed
Manchester encoded data
Txd
SFD
DATA
8 bit width "ALL_ONE" Preamble
Manchester encoded data
Txd
SFD
DATA
8 bit width "ALL_ZERO" Preamble Manchester encoded data
Txd
SFD
DATA
8 bit width "ZERO_ONE" Preamble
Manchester encoded data
Txd
SFD
DATA
8 bit width "ONE_ZERO" Preamble
A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 31-10 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start 304
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of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the SYNC field in the US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the SYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the SYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information. Figure 31-10. Start Frame Delimiter
Preamble Length is set to 0 SFD Manchester encoded data Txd DATA One bit start frame delimiter SFD Manchester encoded data Txd DATA
SFD Manchester encoded data Txd
Command Sync start frame delimiter DATA Data Sync start frame delimiter
Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken.
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Figure 31-11. Bit Resynchronization
Oversampling 16x Clock RXD Sampling point Expected edge Tolerance
Synchro. Error
Synchro. Jump
Sync Jump
Synchro. Error
31.6.3.3
Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. The number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 31-12 and Figure 31-13 illustrate start detection and character reception when USART operates in asynchronous mode.
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Figure 31-12. Asynchronous Start Detection
Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling
Start Detection RXD Sampling
1
2
3
4
5
6
01 Start Rejection
7
2
3
4
Figure 31-13. Asynchronous Character Reception
Example: 8-bit, Parity Enabled
Baud Rate Clock RXD Start Detection
16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
31.6.3.4
Manchester Decoder When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See Figure 31-9 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 31-14.. The sample pulse rejection mechanism applies.
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Figure 31-14. Asynchronous Start Bit Detection
Sampling Clock (16 x) Manchester encoded data
Txd Start Detection 1 2 3 4
The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 31-15 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. See Figure 31-16 for an example of Manchester error detection during data phase. Figure 31-15. Preamble Pattern Mismatch
Preamble Mismatch Manchester coding error Preamble Mismatch invalid pattern
Manchester encoded data
Txd
SFD
DATA
Preamble Length is set to 8
Figure 31-16. Manchester Error Flag
Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area
sampling points
Preamble subpacket and Start Frame Delimiter were successfully decoded
Manchester Coding Error detected
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When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. The decoder does not perform pipelining of incoming data stream. Thus when unipolar mode is enabled, it is highly recommended to assure consistency between start frame delimiter (or preamble) waveform and default active level. Example: when the line idles, the logic level is one; to synchronize and avoid confusion, a zero-to-one transition is mandatory. 31.6.3.5 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 31-17. Figure 31-17. Manchester Encoded Characters RF Transmission
Fup frequency Carrier ASK/FSK Upstream Receiver
Upstream Emitter
LNA VCO RF filter Demod
Serial Configuration Interface
control Fdown frequency Carrier bi-dir line ASK/FSK downstream transmitter
Manchester decoder
USART Receiver
Downstream Receiver
Manchester encoder PA RF filter Mod VCO
USART Emitter
control
The USART module is configured as a Manchester encoder/decoder. It is also highly recommended to use PIO interface to access RF receiver configuration registers. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 31-18 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the mod-
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ulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 31-19. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 31-18. ASK Modulator Output
1 NRZ stream Manchester encoded data default polarity unipolar output ASK Modulator Output Uptstream Frequency F0 0 0 1
Txd
Figure 31-19. FSK Modulator Output
1 NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 0 0 1
Txd
31.6.3.6
Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 31-20 illustrates a character reception in synchronous mode.
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Figure 31-20. Synchronous Mode Character Reception
Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock
RXD Sampling
Start
D0
D1
D2
D3
D4
D5
D6
D7 Parity Bit
Stop Bit
31.6.3.7
Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
Figure 31-21. Receiver Status
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
RSTSTA = 1
Write US_CR Read US_RHR
RXRDY OVRE
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31.6.3.8
Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see "Multidrop Mode" on page 313. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 31-6 shows an example of the parity bit for the character 0x41 (character ASCII "A") depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 31-6.
Character A A A A A
Parity Bit Examples
Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 31-22 illustrates the parity bit status setting and clearing.
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Figure 31-22. Parity Error
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit
RSTSTA = 1
Write US_CR PARE
RXRDY
31.6.3.9
Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0.
31.6.3.10
Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 31-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted.
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Figure 31-23. Timeguard Operations
TG = 4 Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
TG = 4
Write US_THR TXRDY
TXEMPTY
Table 31-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 31-7. Maximum Timeguard Length Depending on Baud Rate
Bit time s 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21
Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200
31.6.3.11
Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. The user can either:
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* Obtain an interrupt when a time-out is detected after having received at least one character. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. * Obtain a periodic interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 31-24 shows the block diagram of the Receiver Time-out feature. Figure 31-24. Receiver Time-out Block Diagram
Baud Rate Clock TO
1 STTTO
D
Q
Clock
16-bit Time-out Counter Load
16-bit Value = TIMEOUT
Character Received RETTO
Clear
0
Table 31-8 gives the maximum time-out period for some standard baud rates. Table 31-8. Maximum Time-out Period
Bit Time s 1 667 833 417 208 104 69 52 35 30 18 17 5 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 1 170 1 138 328
Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 56000 57600 200000
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31.6.3.12
Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 31-25. Framing Error Status
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
RSTSTA = 1
Write US_CR FRAME
RXRDY
31.6.3.13
Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored.
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After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 31-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 31-26. Break Transmission
Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Break Transmission STPBRK = 1
End of Break
STTBRK = 1 Write US_CR TXRDY
TXEMPTY
31.6.3.14
Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.
31.6.3.15
Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 31-27. Figure 31-27. Connection with a Remote Device for Hardware Handshaking
USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
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The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 31-28 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 31-28. Receiver Behavior when Operating with Hardware Handshaking
RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1
Figure 31-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 31-29. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
31.6.4
ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1.
31.6.4.1
ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see "Baud Rate Generator" on page 297). The USART connects to a smart card as shown in Figure 31-30. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only
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when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 31-30. Connection of a Smart Card to the USART
USART SCK TXD CLK I/O Smart Card
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 31.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 31-31. If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 31-32. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error.
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Figure 31-31. T = 0 Protocol without Parity Error
Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit
Figure 31-32. T = 0 Protocol with Parity Error
Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1
Repetition
Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1.
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Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. 31.6.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). 31.6.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 31-33. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 31-33. Connection to IrDA Transceivers
USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD
IrDA Transceivers
The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed.
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31.6.5.1
IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. "0" is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 31-9. Table 31-9.
Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s
IrDA Pulse Duration
Pulse Duration (3/16) 78.13 s 19.53 s 9.77 s 4.88 s 3.26 s 1.63 s
Figure 31-34 shows an example of character transmission. Figure 31-34. IrDA Modulation
Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1
TXD
Bit Period
3 16 Bit Period
31.6.5.2
IrDA Baud Rate Table 31-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of 1.87% must be met. Table 31-10. IrDA Baud Rate Error
Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 38 400 38 400 CD 2 11 18 22 4 22 36 43 6 33 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% 0.00% 1.38% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 4.88 4.88
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Table 31-10. IrDA Baud Rate Error (Continued)
Peripheral Clock 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13
31.6.5.3
IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 31-35 illustrates the operations of the IrDA demodulator.
Figure 31-35. IrDA Demodulator Operations
MCK
RXD
Counter Value
6
5
4
3
2
6
6
5
4
3
2
1
0
Pulse Accepted
Receiver Input
Pulse Rejected Driven Low During 16 Baud Rate Clock Cycles
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly.
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31.6.6
RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 31-36. Figure 31-36. Typical Connection to a RS485 Bus
USART
RXD
TXD RTS
Differential Bus
The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 31-37 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 31-37. Example of RTS Drive with Timeguard
TG = 4 Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Write US_THR TXRDY
TXEMPTY
RTS
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31.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 31-11 gives the correspondence of the USART signals with modem connection standards. Table 31-11. Circuit References
USART Pin TXD RTS DTR RXD CTS DSR DCD RI V24 2 4 20 3 5 6 8 22 CCITT 103 105 108.2 104 106 107 109 125 Direction From terminal to modem From terminal to modem From terminal to modem From modem to terminal From terminal to modem From terminal to modem From terminal to modem From terminal to modem
The control of the RTS and DTR output pins is performed by witting the Control Register (US_CR) with the RTSDIS, RTSEN, DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable commands force the corresponding pin to its active level, i.e. low. The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. 31.6.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 31.6.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.
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Figure 31-38. Normal Mode Configuration
RXD Receiver
TXD Transmitter
31.6.8.2
Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 31-39. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 31-39. Automatic Echo Mode Configuration
RXD Receiver
TXD Transmitter
31.6.8.3
Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 31-40. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 31-40. Local Loopback Mode Configuration
RXD Receiver
Transmitter
1
TXD
31.6.8.4
Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 3141. The transmitter and the receiver are disabled and have no effect. This mode allows bit-bybit retransmission.
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Figure 31-41. Remote Loopback Mode Configuration
Receiver 1 RXD
TXD Transmitter
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31.7
USART User Interface
USART Memory Map
Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Manchester Encoder Decoder Register Reserved Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR - US_FIDI US_NER - US_IF US_MAN - - Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write Read/Write Read/Write - Read/Write Read-only - Read/Write Read/Write - - Reset State - - - - 0x0 - 0x0 - 0x0 0x0 0x0 - 0x174 - - 0x0 0x0 - -
Table 31-12.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028
0x2C - 0x3C 0x0040 0x0044 0x0048 0x004C 0x0050 0x5C - 0xFC 0x100 - 0x128
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31.7.1 Name: USART Control Register US_CR Write-only
30 - 22 - 14 RSTNACK 6 TXEN 29 - 21 - 13 RSTIT 5 RXDIS 28 - 20 - 12 SENDA 4 RXEN 27 - 19 RTSDIS 11 STTTO 3 RSTTX 26 - 18 RTSEN 10 STPBRK 2 RSTRX 25 - 17 DTRDIS 9 STTBRK 1 - 24 - 16 DTREN 8 RSTSTA 0 -
Access Type:
31 - 23 - 15 RETTO 7 TXDIS
* RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. * RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. * RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. * RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. * TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. * TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. * RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR. * STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted.
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* STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. * STTTO: Start Time-out 0: No effect 1: Starts waiting for a character before clocking the time-out counter. * SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. * RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. * RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. * RETTO: Rearm Time-out 0: No effect 1: Restart Time-out * DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. * DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. * RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. * RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1.
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31.7.2 Name: USART Mode Register US_MR Read/Write
30 - 22 VAR_SYNC 14 CHMODE 7 CHRL 6 5 USCLKS 29 MAN 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 - 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24
Access Type:
31 ONEBIT 23 - 15
18 CLKO 10 PAR 2
16 MSBF 8 SYNC 0
1 USART_MODE
* USART_MODE
USART_MODE 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 x 0 1 0 1 0 1 0 1 0 x Mode of the USART Normal RS485 Hardware Handshaking Modem IS07816 Protocol: T = 0 Reserved IS07816 Protocol: T = 1 Reserved IrDA Reserved
* USCLKS: Clock Selection
USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK / DIV Reserved SCK
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* CHRL: Character Length.
CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits
* SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. * PAR: Parity Type
PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode
* NBSTOP: Number of Stop Bits
NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved
* CHMODE: Channel Mode
CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin.
* MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. * MODE9: 9-bit Character Length 0: CHRL defines character length.
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1: 9-bit character length. * CKLO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. * OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. * INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. * DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. * VAR_SYNC: Variable synchronization of command/data sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on SYNC value. 1: The sync field is updated when a character is written into US_THR register. * MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. * FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). * MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. * ONEBIT: Start Frame Delimiter selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit.
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31.7.3 Name:
USART Interrupt Enable Register US_IER Write-only
30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 MANE 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITERATION 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 - 16 RIIC 8 TIMEOUT 0 RXRDY
Access Type:
31 - 23 - 15 - 7 PARE
* RXRDY: RXRDY Interrupt Enable * TXRDY: TXRDY Interrupt Enable * RXBRK: Receiver Break Interrupt Enable * ENDRX: End of Receive Transfer Interrupt Enable * ENDTX: End of Transmit Interrupt Enable * OVRE: Overrun Error Interrupt Enable * FRAME: Framing Error Interrupt Enable * PARE: Parity Error Interrupt Enable * TIMEOUT: Time-out Interrupt Enable * TXEMPTY: TXEMPTY Interrupt Enable * ITERATION: Iteration Interrupt Enable * TXBUFE: Buffer Empty Interrupt Enable * RXBUFF: Buffer Full Interrupt Enable * NACK: Non Acknowledge Interrupt Enable * RIIC: Ring Indicator Input Change Enable * DSRIC: Data Set Ready Input Change Enable * DCDIC: Data Carrier Detect Input Change Interrupt Enable * CTSIC: Clear to Send Input Change Interrupt Enable * MANE: Manchester Error Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
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31.7.4 Name: USART Interrupt Disable Register US_IDR Write-only
30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 MANE 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITERATION 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 - 16 RIIC 8 TIMEOUT 0 RXRDY
Access Type:
31 - 23 - 15 - 7 PARE
* RXRDY: RXRDY Interrupt Disable * TXRDY: TXRDY Interrupt Disable * RXBRK: Receiver Break Interrupt Disable * ENDRX: End of Receive Transfer Interrupt Disable * ENDTX: End of Transmit Interrupt Disable * OVRE: Overrun Error Interrupt Disable * FRAME: Framing Error Interrupt Disable * PARE: Parity Error Interrupt Disable * TIMEOUT: Time-out Interrupt Disable * TXEMPTY: TXEMPTY Interrupt Disable * ITERATION: Iteration Interrupt Disable * TXBUFE: Buffer Empty Interrupt Disable * RXBUFF: Buffer Full Interrupt Disable * NACK: Non Acknowledge Interrupt Disable * RIIC: Ring Indicator Input Change Disable * DSRIC: Data Set Ready Input Change Disable * DCDIC: Data Carrier Detect Input Change Interrupt Disable * CTSIC: Clear to Send Input Change Interrupt Disable * MANE: Manchester Error Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
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31.7.5 Name:
USART Interrupt Mask Register US_IMR Read-only
30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 MANE 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITERATION 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 - 16 RIIC 8 TIMEOUT 0 RXRDY
Access Type:
31 - 23 - 15 - 7 PARE
* RXRDY: RXRDY Interrupt Mask * TXRDY: TXRDY Interrupt Mask * RXBRK: Receiver Break Interrupt Mask * ENDRX: End of Receive Transfer Interrupt Mask * ENDTX: End of Transmit Interrupt Mask * OVRE: Overrun Error Interrupt Mask * FRAME: Framing Error Interrupt Mask * PARE: Parity Error Interrupt Mask * TIMEOUT: Time-out Interrupt Mask * TXEMPTY: TXEMPTY Interrupt Mask * ITERATION: Iteration Interrupt Mask * TXBUFE: Buffer Empty Interrupt Mask * RXBUFF: Buffer Full Interrupt Mask * NACK: Non Acknowledge Interrupt Mask * RIIC: Ring Indicator Input Change Mask * DSRIC: Data Set Ready Input Change Mask * DCDIC: Data Carrier Detect Input Change Interrupt Mask * CTSIC: Clear to Send Input Change Interrupt Mask * MANE: Manchester Error Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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31.7.6 Name: USART Channel Status Register US_CSR Read-only
30 - 22 DCD 14 - 6 FRAME 29 - 21 DSR 13 NACK 5 OVRE 28 - 20 RI 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITERATION 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANERR 16 RIIC 8 TIMEOUT 0 RXRDY
Access Type:
31 - 23 CTS 15 - 7 PARE
* RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. * TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. * RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. * ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. * ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. * OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. * FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. * PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. 337
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* TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command. * TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There is at least one character in either US_THR or the Transmit Shift Register. * ITERATION: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSIT. 1: Maximum number of repetitions has been reached since the last RSIT. * TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. * RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. * NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. * RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of US_CSR. 1: At least one input change has been detected on the RI pin since the last read of US_CSR. * DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of US_CSR. 1: At least one input change has been detected on the DSR pin since the last read of US_CSR. * DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of US_CSR. 1: At least one input change has been detected on the DCD pin since the last read of US_CSR. * CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. * RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. * DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. * DCD: Image of DCD Input 338
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AT91SAM7X256/128 Preliminary
0: DCD is at 0. 1: DCD is at 1. * CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. * MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA.
339
6120A-ATARM-01-Sep-05
31.7.7 Name:
USART Receive Holding Register US_RHR Read-only
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 RXCHR 0
Access Type:
31 - 23 - 15 RXSYNH 7
* RXCHR: Received Character Last character received if RXRDY is set. * RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command.
31.7.8 Name:
USART Transmit Holding Register US_THR Write-only
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 TXCHR 0
Access Type:
31 - 23 - 15 TXSYNH 7
* TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. * TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.
340
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
31.7.9 Name: USART Baud Rate Generator Register US_BRGR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CD 7 6 5 4 CD 3 2 1 0 27 - 19 - 11 26 - 18 25 - 17 FP 9 24 - 16
Access Type:
31 - 23 - 15
10
8
* CD: Clock Divider
USART_MODE ISO7816 CD OVER = 0 0 1 to 65535 Baud Rate = Selected Clock/16/CD SYNC = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816
* FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8.
341
6120A-ATARM-01-Sep-05
31.7.10 Name:
USART Receiver Time-out Register US_RTOR Read/Write
30 29 28 27 26 25 24
Access Type:
31
- 23 - 15
- 22 - 14
- 21 - 13
- 20 - 12 TO
- 19 - 11
- 18 - 10
- 17 - 9
- 16 - 8
7
6
5
4 TO
3
2
1
0
* TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
31.7.11 Name:
USART Transmitter Timeguard Register US_TTGR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TG 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Access Type:
31 - 23 - 15 - 7
* TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
342
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
31.7.12 Name: USART FI DI RATIO Register US_FIDI Read/Write 0x174
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FI_DI_RATIO 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 FI_DI_RATIO 1 24 - 16 - 8
Access Type: Reset Value :
31 - 23 - 15 - 7
2
0
* FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
31.7.13 Name:
USART Number of Errors Register US_NER Read-only
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 NB_ERRORS 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Access Type:
31 - 23 - 15 - 7
* NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
343
6120A-ATARM-01-Sep-05
31.7.14 Name:
USART Manchester Configuration Register US_MAN Read/Write
30 DRIFT 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 RX_MPOL 20 - 12 TX_MPOL 4 - 27 - 19 26 - 18 RX_PL 11 - 3 10 - 2 TX_PL 9 TX_PP 1 0 8 25 RX_PP 17 16 24
Access Type:
31 - 23 - 15 - 7 -
* TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1 - 15: The Preamble Length is TX_PL x Bit Period * TX_PP: Transmitter Preamble Pattern
TX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (TX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO
* TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. * RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1 - 15: The detected preamble length is RX_PL x Bit Period * RX_PP: Receiver Preamble Pattern detected
RX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (RX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO
344
AT91SAM7X256/128 Preliminary
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AT91SAM7X256/128 Preliminary
* RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. * DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.
345
6120A-ATARM-01-Sep-05
31.7.15 Name:
USART IrDA FILTER Register US_IF Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 IRDA_FILTER 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Access Type:
31 - 23 - 15 - 7
* IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
346
AT91SAM7X256/128 Preliminary
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AT91SAMX256/128 Preliminary
32. Synchronous Serial Controller (SSC)
32.1 Overview
The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC's high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: * CODEC's in master or slave mode * DAC through dedicated serial interface, particularly I2S * Magnetic card reader
347
6120A-ATARM-01-Sep-05
32.2
Block Diagram
Figure 32-1. Block Diagram
ASB
APB Bridge
PDC APB TF TK TD SSC Interface PIO RF RK Interrupt Control RD
PMC
MCK
SSC Interrupt
32.3
Application Block Diagram
Figure 32-2. Application Block Diagram
OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management
Serial AUDIO
Codec
Line Interface
348
AT91SAM9261 Premliminary
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.4 Pin Name List
I/O Lines Description
Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output
Table 32-1.
Pin Name RF RK RD TF TK TD
32.5
32.5.1
Product Dependencies
I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode.
32.5.2
Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register.
32.5.3
32.6
Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2.
349
6120A-ATARM-01-Sep-05
Figure 32-3. SSC Functional Block Diagram
Transmitter
Clock Output Controller
TK
MCK
Clock Divider
TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller
TX clock
Frame Sync Controller
TF
Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register
TD
APB User Interface
Load Shift
Receiver
Clock Output Controller
RK
RK Input TX Clock RF TF Start Selector
Receive Clock RX Clock Controller
Frame Sync Controller
RF
Receive Shift Register Receive Holding Register Receive Sync Holding Register
RD
RX PDC PDC Interrupt Control
Load Shift
AIC
32.6.1
Clock Management The transmitter clock can be generated by: * an external clock received on the TK I/O pad * the receiver clock * the internal clock divider The receiver clock can be generated by: * an external clock received on the RK I/O pad * the transmitter clock * the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers.
350
AT91SAM9261 Premliminary
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.6.1.1 Clock Divider Figure 32-4. Divided Clock Block Diagram
Clock Divider SSC_CMR MCK /2
12-bit Counter
Divided Clock
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 32-5. Divided Clock Generation
Master Clock
Divided Clock DIV = 1 Divided Clock Frequency = MCK/2
Master Clock
Divided Clock DIV = 3 Divided Clock Frequency = MCK/6
Table 32-2.
Maximum MCK / 2 Minimum MCK / 8190
32.6.1.2
Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select 351
6120A-ATARM-01-Sep-05
TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 32-6. Transmitter Clock Management
SSC_TCMR.CKS
SSC_TCMR.CKO
TK
Receiver Clock Divider Clock 0 1 SSC_TCMR.CKI
32.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. Figure 32-7. Receiver Clock Management
TK
Transmitter Clock
SSC_RCMR.CKS
SSC_RCMR.CKO
RK
Transmitter Clock Divider Clock 0 1 SSC_RCMR.CKI Receiver Clock
RK
352
AT91SAM9261 Premliminary
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.6.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: - Master Clock divided by 2 if Receiver Frame Synchro is input - Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: - Master Clock divided by 6 if Transmit Frame Synchro is input - Master Clock divided by 2 if Transmit Frame Synchro is output 32.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See "Start" on page 354. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See "Frame Sync" on page 356. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 32-8. Transmitter Block Diagram
SSC_CR.TXEN
SSC_SR.TXEN
SSC_CR.TXDIS SSC_TFMR.DATDEF
1 RF Transmitter Clock TF SSC_TFMR.MSBF 0
SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD
Start Selector
Transmit Shift Register
SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR
0
1
SSC_TSHR
SSC_TFMR.FSLEN
353
6120A-ATARM-01-Sep-05
32.6.3
Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See "Start" on page 354. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See "Frame Sync" on page 356. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register.
Figure 32-9. Receiver Block Diagram
SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS
RF Receiver Clock
TF
SSC_RFMR.MSBF
SSC_RFMR.DATNB
Start Selector
Receive Shift Register
RD
SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN
SSC_RHR SSC_RFMR.DATLEN
32.6.4
Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: * Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. * Synchronously with the transmitter/receiver * On detection of a falling/rising edge on TF/RF * On detection of a low level/high level on TF/RF * On detection of a level change or an edge on TF/RF
354
AT91SAM9261 Premliminary
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). Figure 32-10. Transmit Start Mode
TK TF (Input)
Start = Low Level on TF
TD (Output) TD (Output)
X
BO
B1 STTDLY
Start = Falling Edge on TF
X
BO
B1 STTDLY X BO B1 STTDLY
Start = High Level on TF
TD (Output) TD (Output) TD (Output) TD (Output) X
Start = Rising Edge on TF
BO
B1 STTDLY
Start = Level Change on TF
X
BO
B1
BO
B1 STTDLY
Start = Any Edge on TF
X
BO
B1
BO
B1 STTDLY
Figure 32-11. Receive Pulse/Edge Start Modes
RK RF (Input)
Start = Low Level on RF
RD (Input) RD (Input)
X
BO
B1 STTDLY
Start = Falling Edge on RF
X
BO
B1 STTDLY X BO B1 STTDLY
Start = High Level on RF
RD (Input) RD (Input) RD (Input) RD (Input) X
Start = Rising Edge on RF
BO
B1 STTDLY
Start = Level Change on RF
X
BO
B1
BO
B1 STTDLY
Start = Any Edge on RF
X
BO
B1
BO
B1 STTDLY
355
6120A-ATARM-01-Sep-05
32.6.5
Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. * Programmable low or high levels during data transfer are supported. * Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
32.6.5.1
Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out.
32.6.5.2
Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). Receive Compare Modes Figure 32-12. Receive Compare Modes
RK
32.6.6
RD (Input)
CMP0
CMP1
CMP2
CMP3 Start
Ignored
B0
B1
B2
FSLEN Up to 16 Bits (4 in This Example)
STDLY
DATLEN
356
AT91SAM9261 Premliminary
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.6.6.1 Compare Functions Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last FSLEN bits received at the FSLEN lower bit of the data contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: * the event that starts the data transfer (START) * the delay in number of bit periods between the start event and the first data bit (STTDLY) * the length of the data (DATLEN) * the number of data to be transferred for each start event (DATNB). * the length of synchronization transferred for each start event (FSLEN) * the bit sense: most or lowest significant bit first (MSBF). Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR.
32.6.7
357
6120A-ATARM-01-Sep-05
Table 32-3.
Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR
Data Frame Registers
Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN SSC_RCMR SSC_RCMR PERIOD STTDLY Up to 512 Up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number of words transmitted in frame Most significant bit first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay
Figure 32-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes
Start PERIOD TF/RF
(1)
Start
FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data
From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored
TD (If FSDEN = 0) RD
DATNB
Note:
1. Example of input on falling edge of TF/RF.
358
AT91SAM9261 Premliminary
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
Figure 32-14. Transmit Frame Format in Continuous Mode
Start
TD
Data From SSC_THR DATLEN
Data From SSC_THR DATLEN
Default
Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR
Note:
1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.
Figure 32-15. Receive Frame Format in Continuous Mode
Start = Enable Receiver
RD
Data To SSC_RHR DATLEN
Data To SSC_RHR DATLEN
Note:
1. STTDLY is set to 0.
32.6.8
Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.
32.6.9
Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC.
359
6120A-ATARM-01-Sep-05
Figure 32-16. Interrupt Block Diagram
SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear
SSC Interrupt
32.7
SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.
Figure 32-17. Audio Application Block Diagram
Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER
Clock SCK Word Select WS
Data SD
MSB Left Channel
LSB
MSB Right Channel
360
AT91SAM9261 Premliminary
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
Figure 32-18. Codec Application Block Diagram
Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC
Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend
Serial Data In
Figure 32-19. Time Slot Application Block Diagram
SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot
CODEC Second Time Slot
Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend
Serial Data in
361
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8 Synchronous Serial Controller (SSC) User Interface
Register Mapping
Register Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Receive Compare 0 Register Receive Compare 1 Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Register Name SSC_CR SSC_CMR - - SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR - - SSC_RSHR SSC_TSHR SSC_RC0R SSC_RC1R SSC_SR SSC_IER SSC_IDR SSC_IMR - - Access Write Read/Write - - Read/Write Read/Write Read/Write Read/Write Read Write - - Read Read/Write Read/Write Read/Write Read Write Write Read - - Reset - 0x0 - - 0x0 0x0 0x0 0x0 0x0 - - - 0x0 0x0 0x0 0x0 0x000000CC - - 0x0 - -
Table 32-4.
Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100- 0x124
362
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.1 Name: Access Type:
31 - 23 - 15 SWRST 7 -
SSC Control Register SSC_CR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 TXDIS 1 RXDIS 24 - 16 - 8 TXEN 0 RXEN
* RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. * RXDIS: Receive Disable 0: No effect. 1: Disables Receive. If a character is currently being received, disables at end of current character reception. * TXEN: Transmit Enable 0: No effect. 1: Enables Transmit if TXDIS is not set. * TXDIS: Transmit Disable 0: No effect. 1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. * SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR.
363
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.2 Name: Access Type:
31 - 23 - 15 - 7
SSC Clock Mode Register SSC_CMR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 DIV 27 - 19 - 11 26 - 18 - 10 DIV 3 2 1 0 25 - 17 - 9 24 - 16 - 8
* DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
364
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.3 Name: Access Type:
31
SSC Receive Clock Mode Register SSC_RCMR Read/Write
30 29 28 PERIOD 23 22 21 20 STDDLY 15 - 7 CKG 14 - 6 13 - 5 CKI 12 STOP 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24
* CKS: Receive Clock Selection
CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock signal RK pin Reserved
* CKO: Receive Clock Output Mode Selection
CKO 0x0 0x1 0x2 0x3-0x7 Receive Clock Output Mode None Continuous Receive Clock Receive Clock only during data transfers Reserved RK pin Input-only Output Output
* CKI: Receive Clock Inversion 0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal.
365
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
* CKG: Receive Clock Gating Selection
CKG 0x0 0x1 0x2 0x3 Receive Clock Gating None, continuous clock Receive Clock enabled only if RF Low Receive Clock enabled only if RF High Reserved
* START: Receive Start Selection
START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RF signal Detection of a high level on RF signal Detection of a falling edge on RF signal Detection of a rising edge on RF signal Detection of any level change on RF signal Detection of any edge on RF signal Compare 0 Reserved
* STOP: Receive Stop Selection 0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. * STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. * PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
366
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.4 Name: Access Type:
31 - 23 - 15 - 7 MSBF
SSC Receive Frame Mode Register SSC_RFMR Read/Write
30 - 22 29 - 21 FSOS 13 - 5 LOOP 28 - 20 27 - 19 26 - 18 FSLEN 12 - 4 11 10 DATNB 3 2 DATLEN 1 0 9 8 25 - 17 24 FSEDGE 16
14 - 6 -
* DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. * LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. * MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. * DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). * FSLEN: Receive Frame Sync Length This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. Pulse length is equal to (FSLEN + 1) Receive Clock periods. Thus, if FSLEN is 0, the Receive Frame Sync signal is generated during one Receive Clock period.
367
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
* FSOS: Receive Frame Sync Output Selection
FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF Pin Input-only Output Output Output Output Output Undefined
* FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection
368
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.5 Name: Access Type:
31
SSC Transmit Clock Mode Register SSC_TCMR Read/Write
30 29 28 PERIOD 23 22 21 20 STTDLY 15 - 7 CKG 14 - 6 13 - 5 CKI 12 - 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24
* CKS: Transmit Clock Selection
CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved
* CKO: Transmit Clock Output Mode Selection
CKO 0x0 0x1 0x2 0x3-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Transmit Clock only during data transfers Reserved TK pin Input-only Output Output
* CKI: Transmit Clock Inversion 0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. * CKG: Transmit Clock Gating Selection
CKG 0x0 0x1 0x2 0x3 Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TF Low Transmit Clock enabled only if TF High Reserved
369
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
* START: Transmit Start Selection
START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 - 0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. Receive start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved
* STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. * PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
370
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.6 Name: Access Type:
31 - 23 FSDEN 15 - 7 MSBF
SSC Transmit Frame Mode Register SSC_TFMR Read/Write
30 - 22 29 - 21 FSOS 13 - 5 DATDEF 28 - 20 27 - 19 26 - 18 FSLEN 12 - 4 11 10 DATNB 3 2 DATLEN 1 0 9 8 25 - 17 24 FSEDGE 16
14 - 6 -
* DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. * DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. * MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. * DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1). * FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. Pulse length is equal to (FSLEN + 1) Transmit Clock periods, i.e., the pulse length can range from 1 to 16 Transmit Clock periods. If FSLEN is 0, the Transmit Frame Sync signal is generated during one Transmit Clock period.
371
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
* FSOS: Transmit Frame Sync Output Selection
FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF Pin Input-only Output Output Output Output Output Undefined
* FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. * FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection
372
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.7 Name: Access Type:
31
SSC Receive Holding Register SSC_RHR Read-only
30 29 28 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
32.8.8 Name:
SSC Transmit Holding Register SSC_THR Write-only
30 29 28 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Access Type:
31
* TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
373
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.9 Name: Access Type:
31 - 23 - 15
SSC Receive Synchronization Holding Register SSC_RSHR Read-only
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RSDAT 7 6 5 4 RSDAT 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* RSDAT: Receive Synchronization Data
32.8.10 Name:
SSC Transmit Synchronization Holding Register SSC_TSHR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TSDAT 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Access Type:
31 - 23 - 15
7
6
5
4 TSDAT
3
2
1
0
* TSDAT: Transmit Synchronization Data
374
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.11 Name: Access Type:
31 - 23 - 15
SSC Receive Compare 0 Register SSC_RC0R Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CP0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 CP0
3
2
1
0
* CP0: Receive Compare Data 0
375
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.12 Name: Access Type:
31 - 23 - 15
SSC Receive Compare 1 Register SSC_RC1R Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CP1 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 CP1
3
2
1
0
* CP1: Receive Compare Data 1
376
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.13 Name: Access Type:
31 - 23 - 15 - 7 RXBUFF
SSC Status Register SSC_SR Read-only
30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 RXEN 9 CP1 1 TXEMPTY 24 - 16 TXEN 8 CP0 0 TXRDY
* TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty. * TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from TSR. 1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. * ENDTX: End of Transmission 0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. * TXBUFE: Transmit Buffer Empty 0: SSC_TCR or SSC_TNCR have a value other than 0. 1: Both SSC_TCR and SSC_TNCR have a value of 0. * RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. * OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. * ENDRX: End of Reception 0: Data is written on the Receive Counter Register or Receive Next Counter Register. 1: End of PDC transfer when Receive Counter Register has arrived at zero. * RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. * CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. * CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register. 377
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
* TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. * RXSYN: Receive Sync 0: An Rx Sync has not occurred since the last read of the Status Register. 1: An Rx Sync has occurred since the last read of the Status Register. * TXEN: Transmit Enable 0: Transmit is disabled. 1: Transmit is enabled. * RXEN: Receive Enable 0: Receive is disabled. 1: Receive is enabled.
378
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.14 Name: Access Type:
31 - 23 - 15 - 7 RXBUFF
SSC Interrupt Enable Register SSC_IER Write-only
30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY
* TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. * TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt. * ENDTX: End of Transmission Interrupt Enable 0: No effect. 1: Enables the End of Transmission Interrupt. * TXBUFE: Transmit Buffer Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Buffer Empty Interrupt * RXRDY: Receive Ready Interrupt Enable 0: No effect. 1: Enables the Receive Ready Interrupt. * OVRUN: Receive Overrun Interrupt Enable 0: No effect. 1: Enables the Receive Overrun Interrupt. * ENDRX: End of Reception Interrupt Enable 0: No effect. 1: Enables the End of Reception Interrupt. * RXBUFF: Receive Buffer Full Interrupt Enable 0: No effect. 1: Enables the Receive Buffer Full Interrupt. * CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. * CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. 379
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
* TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. * RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.
380
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.15 Name: Access Type:
31 - 23 - 15 - 7 RXBUFF
SSC Interrupt Disable Register SSC_IDR Write-only
30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY
* TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. * TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt. * ENDTX: End of Transmission Interrupt Disable 0: No effect. 1: Disables the End of Transmission Interrupt. * TXBUFE: Transmit Buffer Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Buffer Empty Interrupt. * RXRDY: Receive Ready Interrupt Disable 0: No effect. 1: Disables the Receive Ready Interrupt. * OVRUN: Receive Overrun Interrupt Disable 0: No effect. 1: Disables the Receive Overrun Interrupt. * ENDRX: End of Reception Interrupt Disable 0: No effect. 1: Disables the End of Reception Interrupt. * RXBUFF: Receive Buffer Full Interrupt Disable 0: No effect. 1: Disables the Receive Buffer Full Interrupt. * CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. * CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. 381
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
* TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. * RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt.
382
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
32.8.16 Name: Access Type:
31 - 23 - 15 - 7 RXBUF
SSC Interrupt Mask Register SSC_IMR Read-only
30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY
* TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled. * TXEMPTY: Transmit Empty Interrupt Mask 0: The Transmit Empty Interrupt is disabled. 1: The Transmit Empty Interrupt is enabled. * ENDTX: End of Transmission Interrupt Mask 0: The End of Transmission Interrupt is disabled. 1: The End of Transmission Interrupt is enabled. * TXBUFE: Transmit Buffer Empty Interrupt Mask 0: The Transmit Buffer Empty Interrupt is disabled. 1: The Transmit Buffer Empty Interrupt is enabled. * RXRDY: Receive Ready Interrupt Mask 0: The Receive Ready Interrupt is disabled. 1: The Receive Ready Interrupt is enabled. * OVRUN: Receive Overrun Interrupt Mask 0: The Receive Overrun Interrupt is disabled. 1: The Receive Overrun Interrupt is enabled. * ENDRX: End of Reception Interrupt Mask 0: The End of Reception Interrupt is disabled. 1: The End of Reception Interrupt is enabled. * RXBUFF: Receive Buffer Full Interrupt Mask 0: The Receive Buffer Full Interrupt is disabled. 1: The Receive Buffer Full Interrupt is enabled. * CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. * CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. 383
6120A-ATARM-01-Sep-05
AT91SAM9261 Premliminary
* TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. * RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled.
384
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
33. Timer/Counter (TC)
33.1 Overview
The Timer/Counter (TC) includes three identical 16-bit Timer/Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer/Counter block has two global registers which act upon all three (or two) TC channels. The Block Control Register allows the three (or two) channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained.
33.2
Block Diagram
Figure 33-1. Timer/Counter Block Diagram
Parallel I/O Controller TCLK0
TIMER_CLOCK2
TIMER_CLOCK1
TIOA1
TIMER_CLOCK3
TCLK0 TCLK1 TCLK2 TIOA0 TIOB0
TIOA2 TCLK1
XC0 XC1 XC2 TC0XC0S
Timer/Counter Channel 0
TIOA
TIOA0
TIOB
TIMER_CLOCK4 TIMER_CLOCK5
TCLK2
TIOB0
SYNC
INT0
TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S
SYNC
Timer/Counter Channel 1
TIOA
TIOA1
TIOB
TIOB1 INT1
TIOA1 TIOB1
TCLK0 TCLK1 TCLK2 TIOA0 TIOA1
XC0 XC1 XC2 TC2XC2S
Timer/Counter Channel 2
TIOA
TIOA2
TIOB
TIOB2
SYNC
TIOA2 TIOB2
INT2
Timer Counter Advanced Interrupt Controller
385
6120A-ATARM-01-Sep-05
Table 33-1.
Signal Name Description
Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture Mode: Timer/Counter Input Waveform Mode: Timer/Counter Output Capture Mode: Timer/Counter Input Waveform Mode: Timer/Counter Input/output Interrupt Signal Output Synchronization Input Signal
Block/Channel
Channel Signal
TIOB INT SYNC
33.3
Pin Name List
Table 33-2.
Pin Name
TC pin list
Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O
TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2
33.4
33.4.1
Product Dependencies
I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions.
33.4.2
Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer/Counter clock.
33.4.3
Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC.
386
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33.5
33.5.1
Functional Description
TC Description The three channels of the Timer/Counter are independent and identical in operation. The registers for channel programming are listed in Table 33-4 on page 400.
33.5.1.1
16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.
33.5.1.2
Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 33-2. Each channel can independently select an internal or external clock source for its counter: * Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 * External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock
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Figure 33-2. Clock Selection
TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI
Selected Clock
BURST
1
33.5.1.3
Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 33-3. * The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. * The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled.
388
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Figure 33-3. Clock Control
Selected Clock Trigger
CLKSTA
CLKEN
CLKDIS
Q Q S R
S R
Counter Clock
Stop Event
Disable Event
33.5.1.4
TC Operating Modes Each channel can independently operate in two different modes: * Capture Mode provides measurement on signals. * Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger.
33.5.1.5
Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: * Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. * SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. * Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR.
389
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If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 33.5.2 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 33-4 shows the configuration of the TC channel when programmed in Capture Mode. 33.5.2.1 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 33.5.2.2 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
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Figure 33-4. Capture Mode
TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 LDBSTOP BURST Register C Capture Register A SWTRG CLK RESET 16-bit Counter OVF Capture Register B LDBDIS CLKI CLKSTA CLKEN CLKDIS
Q Q S R
S R
1
Compare RC =
AT91SAM7X256/128 Preliminary
SYNC Trig ABETRG ETRGEDG MTIOB Edge Detector LDRA Edge Detector If RA is Loaded LDRB Edge Detector
TC1_SR
CPCTRG
TIOB
ETRGS
COVFS
LOVRS
LDRAS
LDRBS
CPCS
MTIOA If RA is not loaded or RB is Loaded
TC1_IMR
TIOA
Timer/Counter Channel
INT
391
33.5.3
Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 33-5 shows the configuration of the TC channel when programmed in Waveform Operating Mode.
33.5.3.1
Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.
392
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TIMER_CLOCK5 XC0 XC1 XC2
Q
S R
CPCSTOP
Output Controller
WAVSEL EEVT BEEVT EEVTEDG Edge Detector TIOB TC1_IMR TC1_SR ENETRG ETRGS COVFS CPCS CPAS CPBS
Output Controller
6120A-ATARM-01-Sep-05
Figure 33-5. Waveform Mode
TCCLKS CLKSTA TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 CLKI CLKEN CLKDIS ACPC
Q
S
CPCDIS
R
ACPA
MTIOA
AEEVT
TIOA
BURST WAVSEL
Register A
Register B
Register C
AT91SAM7X256/128 Preliminary
ASWTRG Compare RA = Compare RB = Compare RC =
1
16-bit Counter
CLK RESET OVF
SWTRG
BCPC SYNC Trig BCPB MTIOB
TIOB
BSWTRG
Timer/Counter Channel
INT
393
33.5.3.2
WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 33-6. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 33-7. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 33-6. WAVSEL= 00 without trigger
Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
394
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Figure 33-7. WAVSEL= 00 with trigger
Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
33.5.3.3
WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 33-8. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 33-9. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR).
395
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Figure 33-8. WAVSEL = 10 Without Trigger
Counter Value 0xFFFF Counter cleared by compare match with RC RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 33-9. WAVSEL = 10 With Trigger
Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger
RA
Waveform Examples TIOB
Time
TIOA
33.5.3.4
WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 33-10. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-11.
396
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RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 33-10. WAVSEL = 01 Without Trigger
Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 33-11. WAVSEL = 01 With Trigger
Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF
Counter incremented by trigger
RA
Waveform Examples TIOB
Time
TIOA
33.5.3.5
WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 33-12.
397
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A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-13. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 33-12. WAVSEL = 11 Without Trigger
Counter Value 0xFFFF Counter decremented by compare match with RC RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 33-13. WAVSEL = 11 With Trigger
Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger
RA
Waveform Examples TIOB
Time
TIOA
33.5.3.6
External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger.
398
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The parameter EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 33.5.3.7 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR.
399
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33.6
33.6.1
Timer/Counter (TC) User Interface
Global Register Mapping Timer/Counter (TC) Global Register Map
Channel/Register TC Channel 0 TC Channel 1 TC Channel 2 TC Block Control Register TC Block Mode Register TC_BCR TC_BMR Name Access See Table 33-4 See Table 33-4 See Table 33-4 Write-only Read/Write - 0 Reset Value
Table 33-3.
Offset 0x00 0x40 0x80 0xC0 0xC4
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in Table 33-4. The offset of each of the channel registers in Table 33-4 is in relation to the offset of the corresponding channel as mentioned in Table 33-4. 33.6.2 Channel Memory Mapping Timer/Counter (TC) Channel Memory Mapping
Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Read only if WAVE = 0 Name TC_CCR TC_CMR - - TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR - Access Write-only Read/Write - - Read-only Read/Write
(1)
Table 33-4.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30-0xFC Note: 1.
Reset Value - 0 - - 0 0 0 0 0 - - 0 -
Read/Write(1) Read/Write Read-only Write-only Write-only Read-only -
400
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33.6.3 TC Block Control Register TC_BCR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 SYNC
Register Name: Access Type:
31 - 23 - 15 - 7 -
* SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
401
6120A-ATARM-01-Sep-05
33.6.4
TC Block Mode Register TC_BMR Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 TC2XC2S 28 - 20 - 12 - 4 27 - 19 - 11 - 3 TCXC1S 26 - 18 - 10 - 2 25 - 17 - 9 - 1 TC0XC0S 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* TC0XC0S: External Clock Signal 0 Selection
TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2
* TC1XC1S: External Clock Signal 1 Selection
TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2
* TC2XC2S: External Clock Signal 2 Selection
TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1
402
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33.6.5 TC Channel Control Register TC_CCR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SWTRG 25 - 17 - 9 - 1 CLKDIS 24 - 16 - 8 - 0 CLKEN
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. * CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. * SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started.
403
6120A-ATARM-01-Sep-05
33.6.6
TC Channel Mode Register: Capture Mode TC_CMR Read/Write
30 - 22 - 14 CPCTRG 6 LDBSTOP 29 - 21 - 13 - 5 BURST 28 - 20 - 12 - 4 11 - 3 CLKI 27 - 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 - 18 25 - 17 LDRA 8 24 - 16
Register Name: Access Type:
31 - 23 - 15 WAVE = 0 7 LDBDIS
* TCCLKS: Clock Selection
TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2
* CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection
BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock.
* LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. * LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs.
404
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* ETRGEDG: External Trigger Edge Selection
ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge
* ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. * CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. * WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). * LDRA: RA Loading Selection
LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA
* LDRB: RB Loading Selection
LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA
405
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33.6.7
TC Channel Mode Register: Waveform Mode TC_CMR Read/Write
30 BSWTRG 23 ASWTRG 15 14 WAVSEL 6 CPCSTOP 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24
Register Name: Access Type:
31
WAVE = 1 7 CPCDIS
* TCCLKS: Clock Selection
TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2
* CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection
BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock.
* CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. * CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC.
406
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* EEVTEDG: External Event Edge Selection
EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge
* EEVT: External Event Selection
EEVT 0 0 1 1 Note: 1. 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input(1) output output output
If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
* ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. * WAVSEL: Waveform Selection
WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare
* WAVE = 1 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. * ACPA: RA Compare Effect on TIOA
ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle
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* ACPC: RC Compare Effect on TIOA
ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle
* AEEVT: External Event Effect on TIOA
AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle
* ASWTRG: Software Trigger Effect on TIOA
ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle
* BCPB: RB Compare Effect on TIOB
BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle
* BCPC: RC Compare Effect on TIOB
BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle
408
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* BEEVT: External Event Effect on TIOB
BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle
* BSWTRG: Software Trigger Effect on TIOB
BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle
409
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33.6.8
TC Counter Value Register TC_CV Read-only
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CV 7 6 5 4 CV 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* CV: Counter Value CV contains the counter value in real time.
410
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33.6.9 TC Register A TC_RA Read-only if WAVE = 0, Read/Write if WAVE = 1
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RA 7 6 5 4 RA 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* RA: Register A RA contains the Register A value in real time.
411
6120A-ATARM-01-Sep-05
33.6.10
TC Register B TC_RB Read-only if WAVE = 0, Read/Write if WAVE = 1
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RB 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
7
6
5
4 RB
3
2
1
0
* RB: Register B RB contains the Register B value in real time.
33.6.11
TC Register C TC_RC Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RC 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
7
6
5
4 RC
3
2
1
0
* RC: Register C RC contains the Register C value in real time.
412
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33.6.12 TC Status Register TC_SR Read-only
30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 MTIOB 10 - 2 CPAS 25 - 17 MTIOA 9 - 1 LOVRS 24 - 16 CLKSTA 8 - 0 COVFS
Register Name: Access Type:
31 - 23 - 15 - 7 ETRGS
* COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. * LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. * CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. * CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. * CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. * LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. * LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. * ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. * CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. 413
6120A-ATARM-01-Sep-05
* MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. * MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
414
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33.6.13 TC Interrupt Enable Register TC_IER Write-only
30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
Register Name: Access Type:
31 - 23 - 15 - 7 ETRGS
* COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. * LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. * CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. * CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. * CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. * LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. * LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. * ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt.
415
6120A-ATARM-01-Sep-05
33.6.14
TC Interrupt Disable Register TC_IDR Write-only
30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
Register Name: Access Type:
31 - 23 - 15 - 7 ETRGS
* COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. * LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). * CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). * CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). * CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. * LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). * LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). * ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt.
416
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33.6.15 TC Interrupt Mask Register TC_IMR Read-only
30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
Register Name: Access Type:
31 - 23 - 15 - 7 ETRGS
* COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. * LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. * CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. * CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. * CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. * LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. * LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. * ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled.
417
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418
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34. Pulse Width Modulation Controller (PWM)
34.1 Overview
The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock. All PWM macrocell accesses are made through APB mapped registers. Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
34.2
Block Diagram
Figure 34-1. Pulse Width Modulation Controller Block Diagram
PWM Controller
PWMx Channel
Period Update Duty Cycle Comparator
PWMx PWMx
Clock Selector
Counter
PIO
PWM0 Channel
Period Update Duty Cycle Comparator
PWM0 PWM0
Clock Selector
MCK
Counter
PMC
Clock Generator
APB Interface
Interrupt Generator
AIC
APB
419
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34.3
I/O Lines Description
Each channel outputs one waveform on one external I/O line. Table 34-1.
Name PWMx
I/O Line Description
Description Type Output
PWM Waveform Output for channel x
34.4
34.4.1
Product Dependencies
I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.
34.4.2
Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. Configuring the PWM does not require the PWM clock to be enabled.
34.4.3
Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the PWM interrupt requires the AIC to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode.
420
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34.5 Functional Description
The PWM macrocell is primarily composed of a clock generator module and 4 channels. * Clocked by the system clock, MCK, the clock generator module provides 13 clocks. * Each channel can independently choose one of the clock generator outputs. * Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 34.5.1 PWM Clock Generator Figure 34-2. Functional View of the Clock Generator Block Diagram
MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024
Divider A
clkA
PREA
DIVA
PWM_MR
Divider B
clkB
PREB
DIVB
PWM_MR
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks: * a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024 * two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB
421
6120A-ATARM-01-Sep-05
Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR). After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock "clk". This situation is also true when the PWM master clock is turned off through the Power Management Controller. 34.5.2 34.5.2.1 PWM Channel Block Diagram Figure 34-3. Functional View of the Channel Block Diagram
Inputs from clock generator Channel Clock Selector Inputs from APB Bus Internal Counter Comparator PWMx output waveform
Each of the 4 channels is composed of three blocks: * A clock selector which selects one of the clocks provided by the clock generator described in Section 34.5.1 "PWM Clock Generator", on page 421. * An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is 16 bits. * A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration. 34.5.2.2 Waveform Properties The different properties of output waveforms are: * the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0. * the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. - If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be claculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
( X x CPRD ) ------------------------------MCK
422
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By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( CRPD x DIVA ) ------------------------------------------ or ( CRPD x DIVAB ) ---------------------------------------------MCK MCK
If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
( 2 x X x CPRD ) -----------------------------------------MCK
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( 2 x CPRD x DIVA ) ) ----------------------------------------------------- or ( 2 x CPRD x DIVB ----------------------------------------------------MCK MCK
* the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left aligned then: ( period - 1 fchannel_x_clock x CDTY ) duty cycle = ----------------------------------------------------------------------------------------------------------period If the waveform is center aligned, then: ( ( period 2 ) - 1 fchannel_x_clock x CDTY ) uty cycle = ---------------------------------------------------------------------------------------------------------------------------( period 2 ) * the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level. * the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned. Figure 34-4. Non Overlapped Center Aligned Waveforms(1)
No overlap
PWM0
PWM1
Period
Note:
1. See Figure 34-5 on page 425 for a detailed description of center aligned waveforms.
423
6120A-ATARM-01-Sep-05
When center aligned, the internal channel counter increases up to CPRD and decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel. Waveforms are fixed at 0 when: * CDTY = CPRD and CPOL = 0 * CDTY = 0 and CPOL = 1 Waveforms are fixed at 1 (once the channel is enabled) when: * CDTY = 0 and CPOL = 0 * CDTY = CPRD and CPOL = 1 The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled.
424
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Figure 34-5. Waveform Properties
PWM_MCKx
CHIDx(PWM_SR)
CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1
PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx)
Period Output Waveform PWMx CPOL(PWM_CMRx) = 0
Output Waveform PWMx CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx)
Left Aligned CALG(PWM_CMRx) = 0
Period Output Waveform PWMx CPOL(PWM_CMRx) = 0
Output Waveform PWMx CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
425
6120A-ATARM-01-Sep-05
34.5.3 34.5.3.1
PWM Controller Operations Initialization Before enabling the output channel, this channel must have been configured by the software application: * Configuration of the clock generator if DIVA and DIVB are required * Selection of the clock for each channel (CPRE field in the PWM_CMRx register) * Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) * Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained below. * Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as explained below. * Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register) * Enable Interrupts (Writing CHIDx in the PWM_IER register) * Enable the PWM channel (Writing CHIDx in the PWM_ENA register) It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register. * In such a situation, all channels may have the same clock selector configuration and the same period specified.
34.5.3.2
Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.
34.5.3.3
Changing the Duty Cycle or the Period It is possible to modulate the output waveform duty cycle or period. To prevent an unexpected output waveform when modifying the waveform parameters while the channel is still enabled, PWM_CPRDx and PWM_CDTYx registers are double buffered. The user can write a new period value or duty cycle value in the update register (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. According to the CPD field in the PWM_CMRx register, PWM_CUPDx either updates the PWM_CPRDx or PWM_CDTYx.
426
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Figure 34-6. Synchronized Period or Duty Cycle Update
User's Writing
PWM_CUPDx Value
1
0
PWM_CMRx. CPD
PWM_CPRDx
PWM_CDTYx
End of Cycle
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level. The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the enabled channel(s). See Figure 34-7. The second method uses an Interrupt Service Routine associated with the PWM channel.
Note: Reading the PWM_ISR register automatically clears CHIDx flags.
Figure 34-7. Polling Method
PWM_ISR Read Acknowledgement and clear previous register state
Writing in CPD field Update of the Period or Duty Cycle
CHIDx = 1
YES Writing in PWM_CUPDx The last write has been taken into account
Note:
Polarity and alignment can be modified only when the channel is disabled.
427
6120A-ATARM-01-Sep-05
34.5.3.4
Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.
428
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34.6 Pulse Width Modulation Controller (PWM) User Interface
Pulse Width Modulation Controller (PWM) Register Mapping
Register PWM Mode Register PWM Enable Register PWM Disable Register PWM Status Register PWM Interrupt Enable Register PWM Interrupt Disable Register PWM Interrupt Mask Register PWM Interrupt Status Register Reserved Reserved Channel 0 Mode Register Channel 0 Duty Cycle Register Channel 0 Period Register Channel 0 Counter Register Channel 0 Update Register Reserved Channel 1 Mode Register Channel 1 Duty Cycle Register Channel 1 Period Register Channel 1 Counter Register Channel 1 Update Register ... PWM_CMR1 PWM_CDTY1 PWM_CPRD1 PWM_CCNT1 PWM_CUPD1 ... Read/Write Read/Write Read/Write Read-only Write-only ... 0x0 0x0 0x0 0x0 ... PWM_CMR0 PWM_CDTY0 PWM_CPRD0 PWM_CCNT0 PWM_CUPD0 Read/Write Read/Write Read/Write Read-only Write-only 0x0 0x0 0x0 0x0 Name PWM_MR PWM_ENA PWM_DIS PWM_SR PWM_IER PWM_IDR PWM_IMR PWM_ISR - Access Read/Write Write-only Write-only Read-only Write-only Write-only Read-only Read-only - Peripheral Reset Value 0 0 0 0 -
Table 34-2.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x4C - 0xFC
0x100 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 ... 0x220 0x224 0x228 0x22C 0x230 ...
429
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34.6.1
PWM Mode Register PWM_MR Read/Write
30 - 22 29 - 21 28 - 20 DIVB 15 - 7 14 - 6 13 - 5 12 - 4 DIVA 11 10 PREA 3 2 1 0 9 8 27 26 PREB 19 18 17 16 25 24
Register Name: Access Type:
31 - 23
* DIVA, DIVB: CLKA, CLKB Divide Factor
DIVA, DIVB 0 1 2-255 CLKA, CLKB CLKA, CLKB clock is turned off CLKA, CLKB clock is clock selected by PREA, PREB CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
* PREA, PREB
PREA, PREB 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Other 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK. MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Reserved Divider Input Clock
430
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34.6.2 PWM Enable Register PWM_ENA Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.
34.6.3
PWM Disable Register PWM_DIS Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x.
431
6120A-ATARM-01-Sep-05
34.6.4
PWM Status Register PWM_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
34.6.5
PWM Interrupt Enable Register PWM_IER Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x.
432
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34.6.6 PWM Interrupt Disable Register PWM_IDR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
433
6120A-ATARM-01-Sep-05
34.6.7
PWM Interrupt Mask Register PWM_IMR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled. 34.6.8 PWM Interrupt Status Register PWM_ISR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
434
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34.6.9 PWM Channel Mode Register PWM_CMRx Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 26 - 18 - 10 CPD 2 CPRE 25 - 17 - 9 CPOL 1 24 - 16 - 8 CALG 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CPRE: Channel Pre-scaler
CPRE 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Other 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 CLKA CLKB Reserved Channel Pre-scaler
* CALG: Channel Alignment 0 = The period is left aligned. 1 = The period is center aligned. * CPOL: Channel Polarity 0 = The output waveform starts at a low level. 1 = The output waveform starts at a high level. * CPD: Channel Update Period 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1 = Writing to the PWM_CUPDx will modify the period at the next period start event. 435
6120A-ATARM-01-Sep-05
34.6.10
PWM Channel Duty Cycle Register PWM_CDTYx Read/Write
30 29 28 CDTY 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 CDTY
19
18
17
16
15
14
13
12 CDTY
11
10
9
8
7
6
5
4 CDTY
3
2
1
0
Only the first 16 bits (internal channel counter size) are significative. * CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx). 34.6.11 PWM Channel Period Register PWM_CPRDx Read/Write
30 29 28 CPRD 23 22 21 20 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
Only the first 16 bits (internal channel counter size) are significative. * CPRD: Channel Period If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: - By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
( X x CPRD ) ------------------------------MCK
- By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
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( CRPD x DIVA ) ------------------------------------------ or ( CRPD x DIVAB ) ---------------------------------------------MCK MCK
If the waveform is center-aligned, then the output waveform period depends on the counter source clockand can be calculated: - By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
( 2 x X x CPRD ) -----------------------------------------MCK
- By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( 2 x CPRD x DIVA ) ----------------------------------------------------- or ( 2 x CPRD x DIVB ) ----------------------------------------------------MCK MCK
437
6120A-ATARM-01-Sep-05
34.6.12
PWM Channel Counter Register PWM_CCNTx Read-only
30 29 28 CNT 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 CNT
19
18
17
16
15
14
13
12 CNT
11
10
9
8
7
6
5
4 CNT
3
2
1
0
* CNT: Channel Counter Register Internal counter value. This register is reset when: - the channel is enabled (writing CHIDx in the PWM_ENA register). - the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. 34.6.13 PWM Channel Update Register PWM_CUPDx Write-only
30 29 28 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle. Only the first 16 bits (internal channel counter size) are significative.
CPD (PWM_CMRx Register) 0 1 The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the beginning of the next period. The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning of the next period.
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35. USB Device Port (UDP)
35.1 Description
The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of DPR. Table 35-1.
Endpoint Number 0 1 3 3 4 5
USB Endpoint Description
Mnemonic EP0 EP1 EP2 EP3 EP4 EP5 Dual-Bank No Yes Yes No Yes Yes Max. Endpoint Size 8 64 64 64 256 256 Endpoint Type Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt
Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt. Depending on the product, an external signal can be used to send a wake-up to the USB host controller.
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35.2
Block Diagram
Figure 35-1. Block Diagram
Atmel Bridge APB to MCU Bus
USB Device
txoen
MCK UDPCK
U s e r I n t e r f a c e
W r a p p e r
Dual Port RAM FIFO
W r a p p e r
eopn
Serial Interface Engine
12 MHz
txd rxdm rxd rxdp
Embedded USB Transceiver
DP DM
SIE
udp_int
Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain
external_resume
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a 48 MHz clock used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake-up once in system mode. The host is then notified that the device asks for a resume. This optional feature must be also negotiated with the host during the enumeration.
35.3
Product Dependencies
For further details on the USB Device hardware implementation, see the specific Product Properties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are available from the product boundary. Two I/O lines may be used by the application: * One to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the board pull-up on DP must be disabled in order to prevent feeding current to the host. * One to control the board pull-up on DP. Thus, when the device is ready to communicate with the host, it activates its DP pull-up through this control line.
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35.3.1 I/O Lines DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB device peripheral. To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to assign this I/O in input PIO mode. To reserve an I/O line to control the board pull-up, the programmer must first program the PIO controller to assign this I/O in output PIO mode. 35.3.2 Power Management The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz domain). 35.3.3 Interrupt The USB device interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the USB device interrupt requires programming the AIC before configuring the UDP.
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35.4
Typical Connection
Figure 35-2. Board Schematic to Interface USB Device Peripheral
PAm
UDP_CNX
15 k
22 k
3V3
1.5 k
47 k PAn
UDP_PUP
System Reset 27 DM DP 15 pF 15 pF
33 pF 2 1 100 nF
Type B 4 Connector
27
3
UDP_ CNX is an input signal used to check if the host is connected UDP_ PUP is an output signal used to disable pull-up on DP by driving it to 0. Figure 35-2 shows automatic activation of pull-up after reset.
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35.5
35.5.1
Functional Description
USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with an USB device through a set of communication flows.
Figure 35-3. Example of USB V2.0 Full-speed Communication Control
USB Host V2.0 Software Client 1 Software Client 2
Data Flow: Control Transfer Data Flow: Isochronous In Transfer Data Flow: Isochronous Out Transfer
EP0 EP1 EP2 USB Device 2.0 Block 1
Data Flow: Control Transfer Data Flow: Bulk In Transfer Data Flow: Bulk Out Transfer
EP0 EP4 EP5 USB Device 2.0 Block 2
35.5.1.1
USB V2.0 Full-speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device.
Table 35-2.
Transfer Control Isochronous Interrupt Bulk
USB Communication Flow
Direction Bidirectional Unidirectional Unidirectional Unidirectional Bandwidth Not guaranteed Guaranteed Not guaranteed Not guaranteed Endpoint Size 8, 16, 32, 64 1 - 1023 64 8, 16, 32, 64 Error Detection Yes Yes Yes Yes Retrying Automatic No Yes Yes
35.5.1.2
USB Bus Transactions Each transfer results in one or more transactions over the USB bus. There are five kinds of transactions flowing across the bus in packets: 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction 4. Status IN Transaction 5. Status OUT Transaction
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35.5.1.3
USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 35-3. USB Transfer Events * Setup transaction > Data IN transactions > Status OUT transaction
Control Transfers(1) (3)
* Setup transaction > Data OUT transactions > Status IN transaction * Setup transaction > Status IN transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction
Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes:
1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake.
35.5.2 35.5.2.1
Handling Transactions with USB V2.0 Device Peripheral Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: * The USB device automatically acknowledges the setup packet * RXSETUP is set in the UDP_ CSRx register * An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_ CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO.
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Figure 35-4. Setup Transaction Followed by a Data OUT Transaction
Setup Received Setup Handled by Firmware Data Out Received
USB Bus Packets
Setup PID
Data Setup
ACK PID
Data OUT PID
Data OUT
NAK PID
Data OUT PID
Data OUT
ACK PID
RXSETUP Flag
Interrupt Pending
Set by USB Device
Cleared by Firmware Set by USB Device Peripheral
RX_Data_BKO (UDP_CSRx)
FIFO (DPR) Content
XX
Data Setup
XX
Data OUT
35.5.2.2
Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes.
35.5.2.3
Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint's UDP_ CSRx register (TXPKTRDY must be cleared). 2. The microcontroller writes data to be sent in the endpoint's FIFO, writing zero or more byte values in the endpoint's UDP_ FDRx register, 3. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint's UDP_ CSRx register. 4. The microcontroller is notified that the endpoint's FIFO has been released by the USB device when TXCOMP in the endpoint's UDP_ CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set.
Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer.
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Figure 35-5. Data IN Transfer for Non Ping-pong Endpoint
Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus
USB Bus Packets
Data IN PID
Data IN 1
ACK PID
Data IN PID
NAK PID
Data IN PID
Data IN 2
ACK PID
TXPKTRDY Flag (UDP_CSRx) Cleared by USB Device Interrupt Pending TXCOMP Flag (UDP_CSRx) Cleared by Firmware Start to Write Data Payload in FIFO Set by the Firmware Data Payload Written in FIFO Interrupt Pending
FIFO (DPR) Content
Data IN 1
Load In Progress
Data IN 2
Load In Progress
35.5.2.4
Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. To be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 35-6. Bank Swapping Data IN Transfer for Ping-pong Endpoints
Microcontroller Write Bank 0 Endpoint 1 USB Device Read USB Bus
1st Data Payload
Read and Write at the Same Time
2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1
Data IN Packet 1st Data Payload
Data IN Packet 2nd Data Payload
Bank 0 Endpoint 1
Data IN Packet 3rd Data Payload
When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions:
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1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint's UDP_ CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint's UDP_ FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint's UDP_ CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint's UDP_ FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint's UDP_ CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent rising TXPKTRDY in the endpoint's UDP_ CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 35-7. Data IN Transfer for Ping-pong Endpoint
Microcontroller Load Data IN Bank 0
Microcontroller Load Data IN Bank 1 USB Device Send Bank 0
Microcontroller Load Data IN Bank 0 USB Device Send Bank 1
USB Bus Packets
Data IN PID
Data IN
ACK PID
Data IN PID
Data IN
ACK PID
TXPKTRDY Flag (UDP_MCSRx)
Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (UDP_CSRx)
Cleared by USB Device, Data Payload Fully Transmitted Set by USB Device
Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device
Interrupt Cleared by Firmware
FIFO (DPR) Written by Microcontroller Bank 0
Read by USB Device
Written by Microcontroller
FIFO (DPR) Bank 1
Written by Microcontroller
Read by USB Device
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set is too long, some Data IN packets may be NACKed, reducing the bandwidth.
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35.5.2.5
Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes.
35.5.2.6
Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint's UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint's UDP_ CSRx register. 5. The microcontroller carries out data received from the endpoint's memory to its memory. Data received is available by reading the endpoint's UDP_ FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint's UDP_ CSRx register. 7. A new Data OUT packet can be accepted by the USB device.
Figure 35-8. Data OUT Transfer for Non Ping-pong Endpoints
Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload
USB Bus Packets
Data OUT PID
Data OUT 1
ACK PID
Data OUT2 PID
Data OUT2
NAK PID
Data OUT PID
Data OUT2
ACK PID
RX_DATA_BK0 (UDP_CSRx)
Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device
FIFO (DPR) Content
Data OUT 1 Written by USB Device
Data OUT 1 Microcontroller Read
An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO.
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35.5.2.7 Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 35-9. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints
Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus
Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1
Bank 1 Endpoint 1
Data IN Packet nd Data Payload 2
Bank 0 Endpoint 1
Data IN Packet 3rd Data Payload
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint's FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint's UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint's UDP_ CSRx register. 6. The microcontroller transfers out data received from the endpoint's memory to the microcontroller's memory. Data received is made available by reading the endpoint's UDP_ FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint's UDP_ CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint's UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set.
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10. The microcontroller transfers out data received from the endpoint's memory to the microcontroller's memory. Data received is available by reading the endpoint's UDP_ FDRx register. 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint's UDP_ CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 35-10. Data OUT Transfer for Ping-pong Endpoint
Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload
USB Bus Packets
Data OUT PID
Data OUT 1
ACK PID
Data OUT PID
Data OUT 2
ACK PID
Data OUT PID
Data OUT 3
A P
RX_DATA_BK0 Flag (UDP_CSRx)
Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0
Cleared by Firmware
RX_DATA_BK1 Flag (UDP_CSRx)
Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1
Cleared by Firmware Interrupt Pending
FIFO (DPR) Bank 0
Data OUT1 Write by USB Device
Data OUT 1 Read By Microcontroller
Data OUT 3 Write In Progress
FIFO (DPR) Bank 1
Data OUT 2 Write by USB Device
Data OUT 2 Read By Microcontroller
Note:
An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set.
Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 35.5.2.8 Status Transaction A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction.
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Figure 35-11. Control Read and Write Sequences
Setup Stage Data Stage Status Stage
Control Read
Setup TX
Data OUT TX
Data OUT TX
Status IN TX
Setup Stage
Data Stage
Status Stage
Control Write
Setup TX
Data IN TX
Data IN TX
Status OUT TX
Setup Stage
Status Stage
No Data Control
Setup TX
Status IN TX
Notes:
1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data).
35.5.2.9
Status IN Transfer Once a control request has been processed, the device returns a status to the host. This is a zero length Data IN transaction. 1. The microcontroller waits for TXPKTRDY in the UDP_ CSRx endpoint's register to be cleared. (At this step, TXPKTRDY must be cleared because the previous transaction was a setup transaction or a Data OUT transaction.) 2. Without writing anything to the UDP_ FDRx endpoint's register, the microcontroller sets TXPKTRDY. The USB device generates a Data IN packet using DATA1 PID. 3. This packet is acknowledged by the host and TXPKTRDY is set in the UDP_ CSRx endpoint's register.
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Figure 35-12. Data Out Followed by Status IN Transfer.
Host Sends the Last Data Payload to the Device Device Sends a Status IN to the Host
USB Bus Packets
Data OUT PID
Data OUT
NAK PID
Data IN PID
ACK PID
Interrupt Pending RX_DATA_BKO (UDP_CSRx) Cleared by Firmware Set by USB Device Cleared by USB Device TXPKTRDY (UDP_CSRx) Set by Firmware
35.5.2.10
Status OUT Transfer Once a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. This is a zero length Data OUT transaction. 1. The USB device receives a zero length packet. It sets RX_DATA_BK0 flag in the UDP_ CSRx register and acknowledges the zero length packet. 2. The microcontroller is notified that the USB device has received a zero length packet sent by the host polling RX_DATA_BK0 in the UDP_ CSRx register. An interrupt is pending while RX_DATA_BK0 is set. The number of bytes received in the endpoint's UDP_ BCR register is equal to zero. 3. The microcontroller must clear RX_DATA_BK0. Figure 35-13. Data IN Followed by Status OUT Transfer
Device Sends the Last Data Payload to Host USB Bus Packets Device Sends a Status OUT to Host
Data IN PID
Data IN
ACK PID
Data OUT PID
ACK PID Interrupt Pending
RX_DATA_BKO (UDP_CSRx)
Set by USB Device
Cleared by Firmware
TXCOMP (UDP_CSRx) Set by USB Device Cleared by Firmware
35.5.2.11
Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)
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* A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) * To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_ CSRx endpoint's register. 2. The host receives the stall packet. 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. Figure 35-14. Stall Handshake (Data IN Transfer)
USB Bus Packets Data IN PID Stall PID
Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device
Figure 35-15. Stall Handshake (Data OUT Transfer)
USB Bus Packets Data OUT PID Data OUT Stall PID
FORCESTALL
Set by Firmware Interrupt Pending
STALLSENT Set by USB Device
Cleared by Firmware
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35.5.3
Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 35-16. USB Device State Diagram
Attached
Hub Reset or Deconfigured
Hub Configured
Bus Inactive
Powered
Bus Activity Power Interruption
Suspended
Reset
Bus Inactive
Default
Reset Address Assigned Bus Inactive Bus Activity
Suspended
Address
Bus Activity Device Deconfigured Device Configured Bus Inactive
Suspended
Configured
Bus Activity
Suspended
Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 uA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse. The wake-up feature is not mandatory for all devices and must be negotiated with the host.
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35.5.3.1 From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The USB host stops driving a reset state once it has detected the device's pull-up on DP. The unmasked flag ENDBURSES is set in the register UDP_ISR and an interrupt is triggered. The UDP software enables the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. 35.5.3.2 From Default State to Address State After a set address standard device request, the USB host peripheral enters the address state. Before this, it achieves the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STATE, sets its new address, and sets the FEN bit in the UDP_FADDR register. 35.5.3.3 From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. 35.5.3.4 Enabling Suspend When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register. This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks may be switched off. However, the transceiver and the USB peripheral must not be switched off, otherwise the resume is not detected. 35.5.3.5 Receiving a Host Resume In suspend mode, the USB transceiver and the USB peripheral must be powered to detect the RESUME. However, the USB device peripheral may not be clocked as the WAKEUP signal is asynchronous. Once the resume is detected on the bus, the signal WAKEUP in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register. 35.5.3.6 Sending an External Resume The External Resume is negotiated with the host and enabled by setting the ESR bit in the UDP_ GLB_STATE. An asynchronous event on the ext_resume_pin of the peripheral generates a WAKEUP interrupt. On early versions of the USP peripheral, the K-state on the USB line is generated immediately. This means that the USB device must be able to answer to the host very
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quickly. On recent versions, the software sets the RMWUPE bit in the UDP_GLB_STATE register once it is ready to communicate with the host. The K-state on the bus is then generated. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register.
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35.6 USB Device Port (UDP) User Interface
UDP Memory Map
Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint 0 Control and Status Register . . . Endpoint 5 Control and Status Register Endpoint 0 FIFO Data Register . . . Endpoint 5 FIFO Data Register Reserved Transceiver Control Register Reserved UDP_ FDR5 - UDP_ TXVC - Read/Write - Read/Write - 0x0000_0000 - 0x0000_0000 - UDP_CSR5 UDP_ FDR0 Read/Write Read/Write 0x0000_0000 0x0000_0000 Name UDP_ FRM_NUM UDP_ GLB_STAT UDP_ FADDR - UDP_ IER UDP_ IDR UDP_ IMR UDP_ ISR UDP_ ICR - UDP_ RST_EP - UDP_CSR0 Access Read Read/Write Read/Write - Write Write Read Read Write - Read/Write - Read/Write - 0x0000_0000 - 0x0000_1200 0x0000_XX00 Reset State 0x0000_0000 0x0000_0010 0x0000_0100 -
Table 35-4.
Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 . . . See Notes: (1) 0x050 . . . See Notes: (2) 0x070 0x074 0x078 - 0xFC Notes:
1. The addresses of the UDP_ CSRx registers are calculated as: 0x030 + 4(Endpoint Number - 1). 2. The addresses of the UDP_ FDRx registers are calculated as: 0x050 + 4(Endpoint Number - 1).
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35.6.1
UDP Frame Number Register UDP_ FRM_NUM Read-only
30 --22 - 14 - 6 29 --21 - 13 - 5 28 --20 - 12 - 4 FRM_NUM 27 --19 - 11 - 3 26 --18 - 10 25 --17 FRM_OK 9 FRM_NUM 1 24 --16 FRM_ERR 8
Register Name: Access Type:
31 --23 - 15 - 7
2
0
* FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). * FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. * FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP.
Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.
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35.6.2 UDP Global State Register UDP_ GLB_STAT Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 RMWUPE 27 - 19 - 11 - 3 RSMINPR 26 - 18 - 10 - 2 ESR 25 - 17 - 9 - 1 CONFG 24 - 16 - 8 - 0 FADDEN
Register Name: Access Type:
31 - 23 - 15 - 7 -
This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. * FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_ FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. * CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. * ESR: Enable Send Resume 0 = Disables the Remote Wake Up sequence. 1 = Remote Wake Up can be processed and the pin send_resume is enabled. * RSMINPR: A Resume Has Been Sent to the Host Read: 0 = No effect. 1 = A Resume has been received from the host during Remote Wake Up feature.
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* RMWUPE: Remote Wake Up Enable 0 = Must be cleared after receiving any HOST packet or SOF interrupt. 1 = Enables the K-state on the USB cable if ESR is enabled.
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35.6.3 UDP Function Address Register UDP_ FADDR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 FADD 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 FEN 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. * FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host.
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35.6.4
UDP Interrupt Enable Register UDP_ IER Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 - 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT
Register Name: Access Type:
31 - 23 - 15 - 7 -
* EP0INT: Enable Endpoint 0 Interrupt * EP1INT: Enable Endpoint 1 Interrupt * EP2INT: Enable Endpoint 2Interrupt * EP3INT: Enable Endpoint 3 Interrupt * EP4INT: Enable Endpoint 4 Interrupt * EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. * RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt. * RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt. * EXTRSM: Enable External Resume Interrupt 0 = No effect. 1 = Enables External Resume Interrupt. * SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. * WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt.
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35.6.5 UDP Interrupt Disable Register UDP_ IDR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 - 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT
Register Name: Access Type:
31 - 23 - 15 - 7 -
* EP0INT: Disable Endpoint 0 Interrupt * EP1INT: Disable Endpoint 1 Interrupt * EP2INT: Disable Endpoint 2 Interrupt * EP3INT: Disable Endpoint 3 Interrupt * EP4INT: Disable Endpoint 4 Interrupt * EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. * RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt. * RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt. * EXTRSM: Disable External Resume Interrupt 0 = No effect. 1 = Disables External Resume Interrupt. * SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt * WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt.
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35.6.6
UDP Interrupt Mask Register UDP_ IMR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 - 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT
Register Name: Access Type:
31 - 23 - 15 - 7 -
* EP0INT: Mask Endpoint 0 Interrupt * EP1INT: Mask Endpoint 1 Interrupt * EP2INT: Mask Endpoint 2 Interrupt * EP3INT: Mask Endpoint 3 Interrupt * EP4INT: Mask Endpoint 4 Interrupt * EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. * RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled. * RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled. * EXTRSM: Mask External Resume Interrupt 0 = External Resume Interrupt is disabled. 1 = External Resume Interrupt is enabled. * SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. * WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled.
Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_ IMR is enabled.
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35.6.7 UDP Interrupt Status Register UDP_ ISR Read-only
30 - 22 - 14 - 29 - 21 - 13 WAKEUP 28 - 20 - 12 ENDBUSRE S 4 EP4INT 27 - 19 - 11 SOFINT 26 - 18 - 10 EXTRSM 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT
Register Name: Access Type:
31 - 23 - 15 -
7 -
6 -
5 EP5INT
3 EP3INT
2 EP2INT
* EP0INT: Endpoint 0 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_ CSR0 bit. * EP1INT: Endpoint 1 Interrupt Status 0 = No Endpoint1 Interrupt pending. 1 = Endpoint1 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR1: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding UDP_ CSR1 bit. * EP2INT: Endpoint 2 Interrupt Status 0 = No Endpoint2 Interrupt pending. 1 = Endpoint2 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR2: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 465
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TXCOMP set to 1 STALLSENT set to 1 EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding UDP_ CSR2 bit. * EP3INT: Endpoint 3 Interrupt Status 0 = No Endpoint3 Interrupt pending. 1 = Endpoint3 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR3: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding UDP_ CSR3 bit. * EP4INT: Endpoint 4 Interrupt Status 0 = No Endpoint4 Interrupt pending. 1 = Endpoint4 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR4: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding UDP_ CSR4 bit. * EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint5 Interrupt pending. 1 = Endpoint5 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR5: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding UDP_ CSR5 bit. * RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. * RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised.
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The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ ICR register. * EXTRSM: External Resume Interrupt Status 0 = No External Resume Interrupt pending. 1 = External Resume Interrupt has been raised. This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus. * SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. * ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. * WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ ICR register.
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35.6.8
UDP Interrupt Clear Register UDP_ ICR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 - 28 - 20 - 12 ENDBURSES 4 - 27 - 19 - 11 SOFINT 3 - 26 - 18 - 10 EXTRSM 2 - 25 - 17 - 9 RXRSM 1 - 24 - 16 - 8 RXSUSP 0 -
Register Name: Access Type:
31 - 23 - 15 - 7 -
* RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. * RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt. * EXTRSM: Clear External Resume Interrupt 0 = No effect. 1 = Clears External Resume Interrupt. * SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. * ENDBURSES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt. * WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt.
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35.6.9 UDP Reset Endpoint Register UDP_ RST_EP Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 EP5 28 - 20 - 12 - 4 EP4 27 - 19 - 11 - 3 EP3 26 - 18 - 10 - 2 EP2 25 - 17 - 9 - 1 EP1 24 - 16 - 8 - 0 EP0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* EP0: Reset Endpoint 0 * EP1: Reset Endpoint 1 * EP2: Reset Endpoint 2 * EP3: Reset Endpoint 3 * EP4: Reset Endpoint 4 * EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear UDP_ CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_ CSRx register.
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35.6.10
UDP Endpoint Control and Status Register UDP_ CSRx [x = 0..5] Read/Write
30 - 22 29 - 21 28 - 20 RXBYTECNT 27 - 19 26 25 RXBYTECNT 17 24
Register Name: Access Type:
31 - 23
18
16
15 EPEDS 7 DIR
14 - 6 RX_DATA_ BK1
13 - 5 FORCE STALL
12 - 4 TXPKTRDY
11 DTGLE 3 STALLSENT ISOERROR
10
9 EPTYPE 1 RX_DATA_ BK0
8
2 RXSETUP
0 TXCOMP
* TXCOMP: Generates an IN packet with data previously written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. * RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0.
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* RXSETUP: Sends STALL to the Host (Control Endpoints) This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_ FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set. * STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints) / ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. * TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = Data values can be written in the FIFO. 1 = Data values can not be written in the FIFO. 471
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Write: 0 = No effect. 1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_ FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. * FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Write-only 0 = No effect. 1 = Sends STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: Notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. * RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO's Bank 1. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. * DIR: Transfer Direction (only available for control endpoints) Read/Write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before UDP_ CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage.
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* EPTYPE[2:0]: Endpoint Type Read/Write
000 001 101 010 110 011 111 Control Isochronous OUT Isochronous IN Bulk OUT Bulk IN Interrupt OUT Interrupt IN
* DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. * EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. * RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_ FDRx register.
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35.6.11
UDP FIFO Data Register UDP_ FDRx [x = 0..5] Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FIFO_DATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_ CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. 35.6.12 UDP Transceiver Control Register UDP_ TXVC Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 TXVDIS 0 -
Register Name: Access Type:
31 - 23 - 15 - 7 -
* TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared.
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36. Analog-to-digital Converter (ADC)
36.1 Overview
The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analog-todigital conversions of up to eight analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These features reduce both power consumption and processor intervention. Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time.
36.2
Block Diagram
Figure 36-1. Analog-to-Digital Converter Block Diagram
Timer Counter Channels
ADC
Trigger Selection
ADTRG
Control Logic
ADC Interrupt
AIC
VDDIN ADVREF ASB AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Successive Approximation Register Analog-to-Digital Converter APB PIO User Interface Peripheral Bridge PDC
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36.3
Signal Description
Table 36-1.
Pin Name VDDIN ADVREF AD0 - AD7 ADTRG
ADC Pin Description
Description Analog power supply Reference voltage Analog input channels External trigger
36.4
36.4.1
Product Dependencies
Power Management The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into Sleep Mode, the Power Management Controller has no effect on the ADC behavior.
36.4.2
Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the ADC interrupt requires the AIC to be programmed first.
36.4.3
Analog Inputs The pins AD0 to AD7 can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND.
36.4.4
I/O Lines The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function.
36.4.5
Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be non-connected.
36.4.6
Conversion Performances For performance and electrical characteristics of the ADC, see Section 41.7 "ADC Characteristics", on page 642.
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36.5
36.5.1
Functional Description
Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the "ADC Mode Register" on page 483 and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in the Product definition section.
36.5.2
Conversion Reference The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion.
36.5.3
Conversion Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0. Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized.
36.5.4
Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel.
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Figure 36-2. EOCx and DRDY Flag Behavior
Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1
Read the ADC_LCDR
CHx (ADC_CHSR) EOCx (ADC_SR) Conversion Time Conversion Time
DRDY (ADC_SR)
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR. The OVRE and GOVRE flags are automatically cleared when ADC_SR is read.
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Figure 36-3. GOVRE and OVREx Flag Behavior
ADTRG CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR ADC_CDR0 ADC_CDR1 Undefined Data Undefined Data Undefined Data Data A Data A Data B Data C Read ADC_SR
Data C Data B
EOC0 (ADC_SR)
Conversion
Conversion
Read ADC_CDR0
EOC1 (ADC_SR)
Conversion
Read ADC_CDR1
GOVRE (ADC_SR) DRDY (ADC_SR) OVRE0 (ADC_SR)
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. 36.5.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the bit TRGEN in the Mode Register (ADC_MR). If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits
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6120A-ATARM-01-Sep-05
for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. 36.5.6 Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode Register ADC_MR. The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the PDC.
Note: The reference voltage pins always remain connected in normal mode as in sleep mode.
36.5.7
ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the SHTIM field. See the section DC Characteristics in the product datasheet.
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36.6 Analog-to-digital Converter (ADC) User Interface
Analog-to-Digital Converter (ADC) Register Mapping
Register Control Register Mode Register Reserved Reserved Channel Enable Register Channel Disable Register Channel Status Register Status Register Last Converted Data Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Data Register 0 Channel Data Register 1 Channel Data Register 2 Channel Data Register 3 Channel Data Register 4 Channel Data Register 5 Channel Data Register 6 Channel Data Register 7 Reserved Name ADC_CR ADC_MR - - ADC_CHER ADC_CHDR ADC_CHSR ADC_SR ADC_LCDR ADC_IER ADC_IDR ADC_IMR ADC_CDR0 ADC_CDR1 ADC_CDR2 ADC_CDR3 ADC_CDR4 ADC_CDR5 ADC_CDR6 ADC_CDR7 - Access Write-only Read/Write - - Write-only Write-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only - Reset State - 0x00000000 - - - - 0x00000000 0x000C0000 0x00000000 - - 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -
Table 36-2.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C
0x50 - 0xFC
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36.6.1
ADC Control Register ADC_CR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
START
SWRST
* SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. * START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion.
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36.6.2 ADC Mode Register ADC_MR Read/Write
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20 19 18
SHTIM
17 16
-
15
-
14
-
13 12 11
STARTUP
10 9 8
-
7
-
6 5 4 3
PRESCAL
2 1 0
-
-
SLEEP
LOWRES
TRGSEL
TRGEN
* TRGEN: Trigger Enable
TRGEN 0 1 Selected TRGEN Hardware triggers are disabled. Starting a conversion is only possible by software. Hardware trigger selected by TRGSEL field is enabled.
* TRGSEL: Trigger Selection
TRGSEL 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected TRGSEL TIOA Ouput of the Timer Counter Channel 0 TIOA Ouput of the Timer Counter Channel 1 TIOA Ouput of the Timer Counter Channel 2 (Reserved on AT91SAM7S32) Reserved Reserved Reserved External trigger Reserved
* LOWRES: Resolution
LOWRES 0 1 Selected Resolution 10-bit resolution 8-bit resolution
* SLEEP: Sleep Mode
SLEEP 0 1 Selected Mode Normal Mode Sleep Mode
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* PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 ) * STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock * SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+1) / ADCClock
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36.6.3 ADC Channel Enable Register ADC_CHER Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
* CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. 36.6.4 ADC Channel Disable Register ADC_CHDR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
* CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
485
6120A-ATARM-01-Sep-05
36.6.5
ADC Channel Status Register ADC_CHSR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
* CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
486
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36.6.6 ADC Status Register ADC_SR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
RXBUFF
11
ENDRX
10
GOVRE
9
DRDY
8
OVRE7
7
OVRE6
6
OVRE5
5
OVRE4
4
OVRE3
3
OVRE2
2
OVRE1
1
OVRE0
0
EOC7
EOC6
EOC5
EOC4
EOC3
EOC2
EOC1
EOC0
* EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. 1 = Corresponding analog channel is enabled and conversion is complete. * OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_SR. 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR. * DRDY: Data Ready 0 = No data has been converted since the last read of ADC_LCDR. 1 = At least one data has been converted and is available in ADC_LCDR. * GOVRE: General Overrun Error 0 = No General Overrun Error occurred since the last read of ADC_SR. 1 = At least one General Overrun Error has occurred since the last read of ADC_SR. * ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR. * RXBUFF: RX Buffer Full 0 = ADC_RCR or ADC_RNCR have a value other than 0. 1 = Both ADC_RCR and ADC_RNCR have a value of 0.
487
6120A-ATARM-01-Sep-05
36.6.7
ADC Last Converted Data Register ADC_LCDR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2 1
LDATA
0
LDATA
* LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
36.6.8
ADC Interrupt Enable Register ADC_IER Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
RXBUFF
11
ENDRX
10
GOVRE
9
DRDY
8
OVRE7
7
OVRE6
6
OVRE5
5
OVRE4
4
OVRE3
3
OVRE2
2
OVRE1
1
OVRE0
0
EOC7
EOC6
EOC5
EOC4
EOC3
EOC2
EOC1
EOC0
* EOCx: End of Conversion Interrupt Enable x * OVREx: Overrun Error Interrupt Enable x * DRDY: Data Ready Interrupt Enable * GOVRE: General Overrun Error Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
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36.6.9 ADC Interrupt Disable Register ADC_IDR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
RXBUFF
11
ENDRX
10
GOVRE
9
DRDY
8
OVRE7
7
OVRE6
6
OVRE5
5
OVRE4
4
OVRE3
3
OVRE2
2
OVRE1
1
OVRE0
0
EOC7
EOC6
EOC5
EOC4
EOC3
EOC2
EOC1
EOC0
* EOCx: End of Conversion Interrupt Disable x * OVREx: Overrun Error Interrupt Disable x * DRDY: Data Ready Interrupt Disable * GOVRE: General Overrun Error Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
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36.6.10
ADC Interrupt Mask Register ADC_IMR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
RXBUFF
11
ENDRX
10
GOVRE
9
DRDY
8
OVRE7
7
OVRE6
6
OVRE5
5
OVRE4
4
OVRE3
3
OVRE2
2
OVRE1
1
OVRE0
0
EOC7
EOC6
EOC5
EOC4
EOC3
EOC2
EOC1
EOC0
* EOCx: End of Conversion Interrupt Mask x * OVREx: Overrun Error Interrupt Mask x * DRDY: Data Ready Interrupt Mask * GOVRE: General Overrun Error Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
36.6.11
ADC Channel Data Register ADC_CDRx Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2 1
DATA
0
DATA
* DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.
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37. Advanced Encryption Standard (AES)
37.1 Overview
The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 80038A Recommendation. It is compatible with all these modes via Peripheral DMA Controller channels, minimizing processor intervention for large buffer transfers. The 128-bit key and input data (and initialization vector for some modes) are each stored in four 32-bit registers (AES_KEYWxR, AES_IDATAxR and AES_IVxR) which are all write-only. As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data is ready to be read out on the four 32-bit output data registers (AES_ODATAxR) or through the PDC channels.
37.2
37.2.1
Product Dependencies
Power Management The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to configure the PMC to enable the AES clock.
37.2.2
Interrupt The AES interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the AES interrupt requires programming the AIC before configuring the AES.
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37.3
Functional Description
The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows selection between the encryption and the decryption processes. The AES is capable of using cryptographic keys of 128 bits to encrypt and decrypt data in blocks of 128 bits. This 128-bit key is defined in the Key Registers (AES_KEYWxR). The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 128-bit data block called the initialization vector (IV), which must be set in the Initialization Vector Registers (AES_IVxR). The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The Initialization Vector Registers are also used by the CTR mode to set the counter value.
37.3.1
Operation Modes The AES supports the following modes of operation: * ECB: Electronic Code Book * CBC: Cipher Block Chaining * OFB: Output Feedback * CFB: Cipher Feedback - CFB8 (CFB where the length of the data segment is 8 bits) - CFB16 (CFB where the length of the data segment is 16 bits) - CFB32 (CFB where the length of the data segment is 32 bits) - CFB64 (CFB where the length of the data segment is 64 bits) - CFB128 (CFB where the length of the data segment is 128 bits) * CTR: Counter The data pre-processing, post-processing and data chaining for the concerned modes are automatically performed. Refer to the NIST Special Publication 800-38A Recommendation for more complete information. These modes are selected by setting the OPMOD field in the AES Mode Register (AES_MR). In CFB mode, five data sizes are possible (8, 16, 32, 64 or 128 bits), configurable by means of the CFBS field in the mode register. (See "AES Mode Register" on page 500.).
37.3.2
Start Modes The SMOD field in the AES Mode Register (AES_MR) allows selection of the encryption (or decryption) start mode.
37.3.2.1
Manual Mode The sequence is as follows: * Write the 128-bit key in the Key Registers (AES_KEYWxR).
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* Write the initialization vector (or counter) in the Initialization Vector Registers (AES_IVxR).
Note: The Initialization Vector Registers concern all modes except ECB.
* Set the bit DATRDY (Data Ready) in the AES Interrupt Enable register (AES_IER), depending on whether an interrupt is required or not at the end of processing. * Write the data to be encrypted/decrypted in the authorized Input Data Registers (See Table 37-1). Table 37-1. Authorized Input Data Registers
Input Data Registers to Write All All All All AES_IDATA1R and AES_IDATA2R AES_IDATA1R AES_IDATA1R AES_IDATA1R All
Operation Mode ECB CBC OFB 128-bit CFB 64-bit CFB 32-bit CFB 16-bit CFB 8-bit CFB CTR Note: Note:
In 64-bit CFB mode, writing to AES_IDATA3R and AES_IDATA4R registers is not allowed and may lead to errors in processing. In 32-, 16- and 8-bit CFB modes, writing to AES_IDATA2R, AES_IDATA3R and AES_IDATA4R registers is not allowed and may lead to errors in processing.
* Set the START bit in the AES Control register AES_CR to begin the encryption or the decryption process. * When processing completes, the bit DATRDY in the AES Interrupt Status Register (AES_ISR) raises. If an interrupt has been enabled by setting the bit DATRDY in AES_IER, the interrupt line of the AES is activated. * When the software reads one of the Output Data Registers (AES_ODATAxR), the DATRDY bit is automatically cleared. 37.3.2.2 Auto Mode The Auto Mode is similar to the manual one, except that in this mode, as soon as the correct number of Input Data registers is written, processing is automatically started without any action in the Control Register. 37.3.2.3 PDC Mode The Peripheral DMA Controller (PDC) can be used in association with the AES to perform an encryption/decryption of a buffer without any action by the software during processing.
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6120A-ATARM-01-Sep-05
In this starting mode, the type of the data transfer (byte, half-word or word) depends on the operation mode. Table 37-2. Data Transfer Type for the Different Operation Modes
Operation Mode ECB CBC OFB CFB 128-bit CFB 64-bit CFB 32-bit CFB 16-bit CFB 8-bit CTR Data Transfer Type (PDC) Word Word Word Word Word Word Half-word Byte Word
The sequence is as follows: * Write the 128-bit key in the Key Registers (AES_KEYWxR). * Write the initialization vector (or counter) in the Initialization Vector Registers (AES_IVxR).
Note: The Initialization Vector Registers concern all modes except ECB.
* Set the Transmit Pointer Register (AES_TPR) to the address where the data buffer to encrypt/decrypt is stored and the Receive Pointer Register (AES_RPR) where it must be encrypted/decrypted.
Note: Transmit and receive buffers can be identical.
* Set the Transmit and the Receive Counter Registers (AES_TCR and AES_RCR) to the same value. This value must be a multiple of the data transfer type size (see Table 37-2).
Note: The same requirements are necessary for the Next Pointer(s) and Counter(s) of the PDC (AES_TNPR, AES_RNPR, AES_TNCR, AES_RNCR).
* If not already done, set the bit ENDRX (or RXBUFF if the next pointers and counters are used) in the AES Interrupt Enable register (AES_IER), depending on whether an interrupt is required or not at the end of processing. * Enable the PDC in transmission and reception to start the processing (AES_PTCR). * When the processing completes, the bit ENDRX (or RXBUFF) in the AES Interrupt Status Register (AES_ISR) raises. If an interrupt has been enabled by setting the corresponding bit in AES_IER, the interrupt line of the AES is activated. 37.3.3 Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining encryption algorithm (CBC-MAC algorithm for example). After each end of encryption/decryption, the output data is available either on the output data registers for Manual and Auto mode or at the address specified in the receive buffer pointer for PDC mode (See Table on page 496). The Last Output Data bit (LOD) in the AES Mode Register (AES_MR) allows retrieval of only the last data of several encryption/decryption processes.
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Therefore, there is no need to define a read buffer in PDC mode. This data is only available on the Output Data Registers (AES_ODATAxR). 37.3.3.1 Manual and Auto Modes * If LOD = 0 The DATRDY flag is cleared when at least one of the Output Data Registers is read (See Figure 37-1). Figure 37-1. Manual and Auto Modes with LOD = 0
Write START bit in AES_CR (Manual mode) or Write AES_IDATAxR register(s) (Auto mode)
Read the AES_ODATAxR
DATRDY
Encryption or Decryption Process
If the user does not want to read the output data registers between each encryption/decryption, the DATRDY flag will not be cleared. If the DATRDY flag is not cleared, the user cannot know the end of the following encryptions/decryptions. * If LOD = 1 The DATRDY flag is cleared when at least one Input Data Register is written, so before the start of a new transfer (See Figure 37-2). No more Output Data Register reads are necessary between consecutive encryptions/decryptions. Figure 37-2. Manual and Auto Modes with LOD = 1
Write START bit in AES_CR (Manual mode) or Write AES_IDATAxR register(s) (Auto mode)
Write AES_IDATAxR register(s)
DATRDY
Encryption or Decryption Process
37.3.3.2
PDC Mode * If LOD = 0 The end of the encryption/decryption is notified by the ENDRX (or RXBUFF) flag rise (see Figure 37-3).
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Figure 37-3. PDC Mode with LOD = 0
Enable PDC Channels (Receive and Transmit Channels)
Multiple Encryption or Decryption Processes ENDRX (or RXBUFF)
* If LOD = 1 The user must first wait for the ENDTX (or TXBUFE) flag to rise, then for DATRDY to ensure that the encryption/decryption is completed (see Figure 37-4). In this case, no receive buffers are required. The output data is only available on the Output Data Registers (AES_ODATAxR). Figure 37-4. PDC Mode with LOD = 1
Enable PDC Channels (only Transmit Channels)
DATRDY Multiple Encryption or Decryption Processes ENDTX (or TXBUFE)
Table 37-3 summarizes the different cases. Table 37-3. Last Output Mode Behavior versus Start Modes
Manual and Auto Modes LOD = 0 DATRDY Flag Clearing Condition(1) At least one Output Data Register must be read In the Output Data Registers LOD = 1 At least one Input Data Register must be written LOD = 0 Not used At the address specified in the Receive Pointer Register (AES_RPR) ENDRX (or RXBUFF) PDC Mode LOD = 1 Managed by the PDC
Encrypted/Decrypted Data Result Location End of Encryption/Decryption Note: 1. 505.
In the Output Data Registers
In the Output Data Registers ENDTX (or TXBUFE) then DATRDY
DATRDY
DATRDY
Depending on the mode, there are other ways of clearing the DATRDY flag. See "AES Interrupt Status Register" on page
Warning: In PDC mode, reading to the Output Data registers before the last data transfer may lead to unpredictable results.
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37.3.4 37.3.4.1 Security Features Countermeasures The AES also features hardware countermeasures that can be useful to protect data against Differential Power Analysis (DPA) attacks. These countermeasures can be enabled through the CTYPE field in the AES Mode Register. This field is write-only, and all changes to it are taken into account if, at the same time, the Countermeasure Key (CKEY field) is correctly written (see "AES Mode Register" on page 500).
Note: Enabling countermeasures has an impact on the AES encryption/decryption throughput.
By default, all the countermeasures are enabled. The best throughput is achieved with all the countermeasures disabled. On the other hand, the best protection is achieved with all of them enabled. The LOADSEED bit in the AES Control Register (AES_CR) allows a new seed to be loaded in the embedded random number generator used for the different countermeasures. 37.3.4.2 Unspecified Register Access Detection When an unspecified register access occurs, the URAD bit in the Interrupt Status Register (AES_ISR) raises. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur: * Input Data Register written during the data processing in PDC mode * Output Data Register read during data processing * Mode Register written during data processing * Output Data Register read during sub-keys generation * Mode Register written during sub-keys generation * Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in the AES_CR control register.
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37.4
Advanced Encryption Standard (AES) User Interface
Table 37-4.
Offset 0x00 0x04 0x08-0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30-0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C
AES 128-bit Register Mapping
Register Control Register Mode Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Key Word 1 Register Key Word 2 Register Key Word 3 Register Key Word 4 Register Reserved Input Data 1 Register Input Data 2 Register Input Data 3 Register Input Data 4 Register Output Data 1 Register Output Data 2 Register Output Data 3 Register Output Data 4 Register Initialization Vector 1 Register Initialization Vector 2 Register Initialization Vector 3 Register Initialization Vector 4 Register Reserved Reserved for the PDC Register Name AES_CR AES_MR - AES_IER AES_IDR AES_IMR AES_ISR AES_KEYW1R AES_KEYW2R AES_KEYW3R AES_KEYW4R - AES_IDATA1R AES_IDATA2R AES_IDATA3R AES_IDATA4R AES_ODATA1R AES_ODATA2R AES_ODATA3R AES_ODATA4R AES_IV1R AES_IV2R AES_IV3R AES_IV4R - - Read/Write Write-only Read/write - Write-only Write-only Read-only Read-only Write-only Write-only Write-only Write-only - Write-only Write-only Write-only Write-only Read-only Read-only Read-only Read-only Write-only Write-only Write-only Write-only - - Reset - 0x0 - - - 0x0 0x0000001E - - - - - - - - - 0x0 0xC01F0000 0x0 0x0 - - - - - -
0x70 - 0xFC 0x100-0x124
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37.4.1 AES Control Register AES_CR Write-only
30 29 28 27 26 25 24
Register name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
LOADSEED
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
SWRST
0
-
-
-
-
-
-
-
START
* START: Start Processing 0 = No effect 1 = Starts manual encryption/decryption process. * SWRST: Software Reset 0 = No effect. 1 = Resets the AES. A software triggered hardware reset of the AES interface is performed. * LOADSEED: Random Number Generator Seed Loading 0 = No effect. 1 = Loads a new seed in the embedded random number generator used for the different countermeasures.
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37.4.2 Name:
AES Mode Register AES_MR Read/write
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21 20 19
CTYPE
18 17 16
CKEY
15 14 13 12
-
11 10
CFBS
9 8
LOD
7 6
OPMOD
5 4
-
3
-
2 1
SMOD
0
PROCDLY
-
-
-
CIPHER
* CIPHER: Processing Mode 0 = Decrypts data. 1 = Encrypts data. * PROCDLY: Processing Delay Processing Time = 12 x ( PROCDLY + 1 ) The Processing Time represents the number of clock cycles that the AES needs in order to perform one encryption/decryption with no countermeasures activated.
Note: The best performance is achieved with PROCDLY equal to 0.
* SMOD: Start Mode
SMOD 0 0 0 1 Description Manual Mode Auto Mode PDC Mode 1 0
* LOD = 0: The encrypted/decrypted data are available at the address specified in the receive pointer registers (AES_RPR, AES_RNPR). * LOD = 1: The encrypted/decrypted data are available in the output data registers.
Reserved
1
1
* OPMOD: Operation Mode
OPMOD 0 0 0 0 1 0 0 1 1 0 others 0 1 0 1 0 Description ECB: Electronic Code Book mode CBC: Cipher Block Chaining mode OFB: Output Feedback mode CFB: Cipher Feedback mode CTR: Counter mode Reserved
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* LOD: Last Output Data Mode 0 = No effect. After each end of encryption/decryption, the output data is available either on the output data registers (Manual and Auto modes), or at the address specified in the receive buffer pointer (PDC mode). In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1 = The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads is necessary between consecutive encryptions/decryptions (see "Last Output Data Mode" on page 494). Warning: In PDC mode, reading to the Output Data registers before the last data encryption/decryption process may lead to unpredictable results. * CFBS: Cipher Feedback Data Size
CFBS 0 0 0 0 1 0 0 1 1 0 Others 0 1 0 1 0 Description 128-bit 64-bit 32-bit 16-bit 8-bit Reserved
* CKEY: Countermeasure Key This field should be written with the value 0xE to allow CTYPE field changes. If the field is written with a different value, changes made through the CTYPE field will not be taken into account.
Note: CKEY field is write-only.
* CTYPE: Countermeasure Type
CTYPE X X X X X X X X 0 1 Note: Note: X X X X X X 0 1 X X X X X X 0 1 X X X X X X 0 1 X X X X X X 0 1 X X X X X X X X Description Countermeasure type 1 is disabled Countermeasure type 1 is enabled Countermeasure type 2 is disabled Countermeasure type 2 is enabled Countermeasure type 3 is disabled Countermeasure type 3 is enabled Countermeasure type 4 is disabled Countermeasure type 4 is enabled Countermeasure type 5 is disabled Countermeasure type 5 is enabled
All the countermeasures are enabled by default. CTYPE field is write-only and can only be modified if CKEY is correctly set.
501
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37.4.3 Name:
AES Interrupt Enable Register AES_IER Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
URAD
0
-
-
-
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
* DATRDY: Data Ready Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable * URAD: Unspecified Register Access Detection Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
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37.4.4 Name: Access Type:
31
AES Interrupt Disable Register AES_IDR Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
URAD
0
-
-
-
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
* DATRDY: Data Ready Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable * URAD: Unspecified Register Access Detection Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
503
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37.4.5 Name:
AES Interrupt Mask Register AES_IMR Read-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
URAD
0
-
-
-
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
* DATRDY: Data Ready Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask * URAD: Unspecified Register Access Detection Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
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37.4.6 Name: Access Type:
31
AES Interrupt Status Register AES_ISR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
URAT
7 6 5 4
-
3
-
2
-
1
URAD
0
-
-
-
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
* DATRDY: Data Ready 0 = Output data is not valid. 1 = Encryption or decryption process is completed. DATRDY is cleared when a Manual encryption/decryption occurs (START bit in AES_CR) or when a software triggered hardware reset of the AES interface is performed (SWRST bit in AES_CR). LOD = 0 (AES_MR): In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Output Data Registers is read. In PDC mode, DATRDY is set and cleared automatically. LOD = 1 (AES_MR): In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Input Data Registers is written. In PDC mode, DATRDY is set and cleared automatically. * ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in AES_RCR or AES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in AES_RCR or AES_RNCR.
Note: This flag must be used only in PDC mode with LOD bit cleared.
* ENDTX: End of TX Buffer 0 = The Transmit Counter Register has not reached 0 since the last write in AES_TCR or AES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in AES_TCR or AES_TNCR.
Note: This flag must be used only in PDC mode with LOD bit set.
* RXBUFF: RX Buffer Full 0 = AES_RCR or AES_RNCR has a value other than 0. Note: 1 =This flag must be used only in PDC mode with LOD bit cleared. Both AES_RCR and AES_RNCR have a value of 0. * TXBUFE: TX Buffer Empty 0 = AES_TCR or AES_TNCR has a value other than 0. 1 = Both AES_TCR and AES_TNCR have a value of 0.
Note: This flag must be used only in PDC mode with LOD bit set.
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* URAD: Unspecified Register Access Detection Status 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. URAD bit is reset only by the SWRST bit in the AES_CR control register. * URAT: Unspecified Register Access Type:
URAT 0 0 0 0 1 1 0 0 1 1 0 0 others 0 1 0 1 0 1 Description Input Data Register written during the data processing in PDC mode. Output Data Register read during the data processing. Mode Register written during the data processing. Output Data Register read during the sub-keys generation. Mode Register written during the sub-keys generation. Write-only register read access. Reserved
Only the last Unspecified Register Access Type is available through the URAT field. URAT field is reset only by the SWRST bit in the AES_CR control register.
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37.4.7 Name: Access Type:
31
AES Key Word x Register AES_KEYWxR Write-only
30 29 28 27 26 25 24
KEYWx
23 22 21 20 19 18 17 16
KEYWx
15 14 13 12 11 10 9 8
KEYWx
7 6 5 4 3 2 1 0
KEYWx
* KEYWx: Key Word x The four 32-bit Key Word registers set the 128-bit cryptographic key used for encryption/decryption. KEYW1 corresponds to the first word of the key and KEYW4 to the last one. These registers are write-only to prevent the key from being read by another application.
37.4.8 Name:
AES Input Data x Register AES_IDATAxR Write-only
30 29 28 27 26 25 24
Access Type:
31
IDATAx
23 22 21 20 19 18 17 16
IDATAx
15 14 13 12 11 10 9 8
IDATAx
7 6 5 4 3 2 1 0
IDATAx
* IDATAx: Input Data Word x The four 32-bit Input Data registers set the 128-bit data block used for encryption/decryption. IDATA1 corresponds to the first word of the data to be encrypted/decrypted, and IDATA4 to the last one. These registers are write-only to prevent the input data from being read by another application.
507
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37.4.9 Name:
AES Output Data x Register AES_ODATAxR Read-only
30 29 28 27 26 25 24
Access Type:
31
ODATAx
23 22 21 20 19 18 17 16
ODATAx
15 14 13 12 11 10 9 8
ODATAx
7 6 5 4 3 2 1 0
ODATAx
* ODATAx: Output Data x The four 32-bit Output Data registers contain the 128-bit data block that has been encrypted/decrypted. ODATA1 corresponds to the first word, ODATA4 to the last one.
37.4.10 Name:
AES Initialization Vector x Register AES_IVxR Write-only
30 29 28 27 26 25 24
Access Type:
31
IVx
23 22 21 20 19 18 17 16
IVx
15 14 13 12 11 10 9 8
IVx
7 6 5 4 3 2 1 0
IVx
* IVx: Initialization Vector x The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input. IV1 corresponds to the first word of the Initialization Vector, IV4 to the last one. These registers are write-only to prevent the Initialization Vector from being read by another application. For CBC, OFB and CFB modes, the Initialization Vector corresponds to the initialization vector. For CTR mode, it corresponds to the counter value.
Note: These registers are not used in ECB mode and must not be written.
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38. Triple Data Encryption System (TDES)
38.1 Description
The Triple Data Encryption Standard (TDES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 46-3 specification. The TDES supports the four different confidentiality modes of operation (ECB, CBC, OFB and CFB), specified in the FIPS (Federal Information Processing Standard) Publication 81 and is compatible with the Peripheral Data Controller channels for all of these modes, minimizing processor intervention for large buffer transfers. The 64-bit long keys and input data (and initialization vector for some modes) are each stored in two 32-bit registers (TDES_KEYxWxR, TDES_IDATAxR and TDES_IVxR) which are both writeonly. As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data is ready to be read out on the two 32-bit output data registers (TDES_ODATAxR) or through the PDC channels.
38.2
38.2.1
Product Dependencies
Power Management The TDES may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the TDES clock.
38.2.2
Interrupt The TDES interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TDES interrupt requires programming the AIC before configuring the TDES.
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38.3
Functional Description
The Data Encryption Standard (DES) and the Triple Data Encryption Algorithm (TDEA) specify FIPS-approved cryptographic algorithms that can be used to protect electronic data. The TDES bit in the TDES Mode Register (TDES_MR) is used to select either the single DES or the Triple DES mode. Encryption (enciphering) converts data to an unintelligible form called ciphertext. Decrypting (deciphering) the ciphertext converts the data back into its original form, called plaintext. The CIPHER bit in the TDES Mode Register is used to choose between encryption and decryption. A DES is capable of using cryptographic keys of 64 bits to encrypt and decrypt data in blocks of 64 bits. This 64-bit key is defined in the Key 1 Word Registers (TDES_KEY1WxR). A TDEA key consists of three DES keys, which is also referred to as a key bundle. These three 64-bit keys are defined, respectively, in the Key 1, 2 and 3 Word Registers (TDES_KEY1WxR, TDES_KEY2WxR and TDES_KEY3WxR). In Triple DES mode (TDESMOD set to 1), the KEYMOD bit in the TDES Mode Register is used to choose between a two- and a three-key algorithm: - In three-key encryption mode, the data is first encrypted with Key 1, then decrypted using Key 2 and then encrypted with Key 3. - In three-key decryption mode, the data is decrypted with Key 3, then encrypted with Key 2 and then decrypted using Key 1. - In two-key encryption mode, the data is first encrypted with Key 1, then decrypted using Key 2 and then encrypted with Key 1. - In two-key decryption mode, the data is decrypted with Key 1, then encrypted with Key 2 and then decrypted using Key 1. The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 64-bit data block called the initialization vector (IV), which must be set in the Initialization Vector Registers (TDES_IVxR). The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message.
38.3.1
Operation Modes The TDES supports the following modes of operation: * ECB: Electronic Code Book * CBC: Cipher Block Chaining * OFB: Output Feedback * CFB: Cipher Feedback - CFB8 (CFB where the length of the data segment is 8 bits) - CFB16 (CFB where the length of the data segment is 16 bits) - CFB32 (CFB where the length of the data segment is 32 bits) - CFB64 (CFB where the length of the data segment is 64 bits) The data pre-processing, post-processing and data chaining for each mode are automatically performed. Refer to the FIPS Publication 81 for more complete information. These modes are selected by setting the OPMOD field in the TDES Mode Register (TDES_MR). In CFB mode, four data sizes are possible (8, 16, 32 and 64 bits), configurable by means of the CFBS field in the mode register. (See "TDES Mode Register" on page 518.).
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38.3.2 Start Modes The SMOD field in the TDES Mode Register (TDES_MR) allows selection of encryption (or decryption) start mode. 38.3.2.1 Manual Mode The sequence is as follows: * Write the 64-bit key(s) in the different Key Word Registers (TDES_KEYxWxR), depending on whether one, two or three keys are required. * Write the initialization vector (or counter) in the Initialization Vector Registers (TDES_IVxR).
Note: The Initialization Vector Registers concern all modes except ECB.
* Set the bit DATRDY (Data Ready) in the TDES Interrupt Enable register (TDES_IER), depending on whether an interrupt is required or not at the end of processing. * Write the data to be encrypted/decrypted in the authorized Input Data Registers (See Table 38-1). Table 38-1. Authorized Input Data Registers
Input Data Registers to Write All All All All TDES_IDATA1R TDES_IDATA1R TDES_IDATA1R
Operation Mode ECB CBC OFB CFB 64-bit CFB 32-bit CFB 16-bit CFB 8-bit Note:
In 32-, 16- and 8-bit CFB mode, writing to TDES_IDATA2R register is not allowed and may lead to errors in processing.
* Set the START bit in the TDES Control register TDES_CR to begin the encryption or the decryption process. * When the processing completes, the bit DATRDY in the TDES Interrupt Status Register (TDES_ISR) raises. If an interrupt has been enabled by setting the bit DATRDY in TDES_IER, the interrupt line of the TDES is activated. * When the software reads one of the Output Data Registers (TDES_ODATAxR), the DATRDY bit is automatically cleared. 38.3.2.2 Auto Mode The Auto Mode is similar to Manual Mode, except that, as soon as the correct number of Input Data registers is written, processing is automatically started without any action in the control register. 38.3.2.3 PDC Mode The Peripheral Data Controller (PDC) can be used in association with the TDES to perform an encryption/decryption of a buffer without any action by the software during processing.
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6120A-ATARM-01-Sep-05
In this starting mode, the type of the data transfer (byte, half-word or word) depends on the operation mode as per Table 38-2. Table 38-2. Data Transfer Type for Different Operation Modes
Operation Mode ECB CBC OFB CFB 64-bit CFB 32-bit CFB 16-bit CFB 8-bit Data Transfer Type (PDC) Word Word Word Word Word Half-word Byte
The sequence is as follows: * Write the 64-bit key(s) in the different Key Word Registers (TDES_KEYxWxR), depending on whether one, two or three keys are required. * Write the initialization vector (or counter) in the Initialization Vector Registers (TDES_IVxR).
Note: The Initialization Vector Registers concern all modes except ECB.
* Set the Transmit Pointer Register (TDES_TPR) to the address where the data buffer to encrypt/decrypt is stored and the Receive Pointer Register (TDES_RPR) where it must be encrypted/decrypted.
Note: Transmit and receive buffers can be identical.
* Set the Transmit and the Receive Counter Registers (TDES_TCR and TDES_RCR) to the same value. This value must be a multiple of the data transfer type size (see Table 38-2).
Note: The same requirements are necessary for the Next Pointer(s) and Counter(s) of the PDC (TDES_TNPR, TDES_RNPR, TDES_TNCR, TDES_RNCR).
* If not already done, set the bit ENDRX (or RXBUFF if the next pointers and counters are used) in the TDES Interrupt Enable register (TDES_IER), depending on whether an interrupt is required or not at the end of processing. * Enable the PDC in transmission and reception to start the processing (TDES_PTCR). * When the processing completes, the bit ENDRX (or RXBUFF) in the TDES Interrupt Status Register (TDES_ISR) raises. If an interrupt has been enabled by setting the corresponding bit in TDES_IER, the interrupt line of the TDES is activated. 38.3.3 Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) using a CBC or a CFB encryption algorithm (See FIPS Publication 81 Appendix F). After each end of encryption/decryption, the output data is available either on the output data registers for Manual and Auto mode or at the address specified in the receive buffer pointer for PDC mode (See Table on page 514). The Last Output Data bit (LOD) in the TDES Mode Register (TDES_MR) retrieves only the last data of several encryption/decryption processes. Therefore, there is no need to define a read buffer in PDC mode. This data is only available on the Output Data Registers (TDES_ODATAxR). 512
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38.3.3.1 Manual and Auto Modes * If LOD = 0: The DATRDY flag is cleared when at least one of the Output Data Registers is read. See Figure 38-1. Figure 38-1. Manual and Auto Modes with LOD = 0
Write START bit in TDES_CR (Manual mode) or Write TDES_IDATAxR register(s) (Auto mode)
Read the TDES_ODATAxR
DATRDY
Encryption or Decryption Process
If the user does not want to read the output data registers between each encryption/decryption, the DATRDY flag will not be cleared. If the DATRDY flag is not cleared, the user will not be informed of the end of the encryptions/decryptions that follow. * If LOD = 1: The DATRDY flag is cleared when at least one Input Data Register is written, before the start of a new transfer. See Figure 38-2. No further Output Data Register reads are necessary between consecutive encryptions/decryptions. Figure 38-2. Manual and Auto Modes with LOD = 1
Write START bit in TDES_CR (Manual mode) or Write TDES_IDATAxR register(s) (Auto mode)
Write TDES_IDATAxR register(s)
DATRDY
Encryption or Decryption Process
38.3.3.2
PDC Mode * If LOD = 0: The end of the encryption/decryption is notified by the ENDRX (or RXBUFF) flag rise See Figure 38-3.
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Figure 38-3. PDC mode with LOD = 0:
Enable PDC Channels (Receive and Transmit Channels)
Multiple Encryption or Decryption Process ENDRX (or RXBUFF)
* If LOD = : The user must first wait for the ENDTX (or TXBUFE) flag rise, then for DATRDY to ensure that the encryption/decryption is completed. See Figure 38-4. In this case, no receive buffers are required. The output data is only available on the Output Data Registers (TDES_ODATAxR). Figure 38-4. PDC Mode with LOD = 1:
Enable PDC Channels (only Transmit Channels)
DATRDY Multiple Encryption or Decryption Process ENDTX (or TXBUFE)
Table 38-3 summarizes the different cases. Table 38-3. Last Output Mode Behavior versus Start Modes
Manual and Auto Modes LOD = 0 DATRDY Flag Clearing Condition(1) At least one Output Data Register must be read LOD = 1 At least one Input Data Register must be written LOD = 0 Not used At the address specified in the Receive Pointer Register (TDES_RPR) ENDRX (or RXBUFF) PDC Mode LOD = 1 Managed by the PDC
Encrypted/Decrypted Data Result Location
In the Output Data Registers
In the Output Data Registers
In the Output Data Registers
End of Encryption/Decryption Note: 1. page 523.
DATRDY
DATRDY
ENDTX (or TXBUFE) then DATRDY
Depending on the mode, there are other ways of clearing the DATRDY flag. See "TDES Interrupt Status Register" on
Warning: In PDC mode, reading to the Output Data registers before the last data transfer may lead to unpredictable result.
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38.3.4 Security Features When an unspecified register access occurs, the URAD bit in the Interrupt Status Register (TDES_ISR) raises. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur: * Input Data Register written during the data processing in PDC mode * Output Data Register read during the data processing * Mode Register written during the data processing * Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in the TDES_CR control register.
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38.4
Triple DES (TDES) User Interface
Table 38-4.
Offset 0x00 0x04 0x08-0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38-0x3C 0x40 0x44 0x48-0x4C 0x50 0x54 0x58-0x5C 0x60 0x64
TDES 128-bit Register Mapping
Register Control Register Mode Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Key 1 Word 1 Register Key 1 Word 2 Register Key 2 Word 1 Register Key 2 Word 2 Register Key 3 Word 1 Register Key 3 Word 2 Register Reserved Input Data 1 Register Input Data 2 Register Reserved Output Data 1 Register Output Data 2 Register Reserved Initialization Vector 1 Register Initialization Vector 2 Register Reserved Reserved for the PDC Register Name TDES_CR TDES_MR - TDES_IER TDES_IDR TDES_IMR TDES_ISR TDES_KEY1W1R TDES_KEY1W2R TDES_KEY2W1R TDES_KEY2W2R TDES_KEY3W1R TDES_KEY3W2R - TDES_IDATA1R TDES_IDATA2R - TDES_ODATA1R TDES_ODATA2R - TDES_IV1R TDES_IV2R - - Read/Write Write-only Read/Write - Write-only Write-only Read-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only - Write-only Write-only - Read-only Read-only - Write-only Write-only - - Reset - 0x2 - - - 0x0 0x0000001E - - - - - - - - - - 0x0 0x0 - - - - -
0x68 - 0xFC 0x100-0x124
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38.4.1 TDES Control Register TDES_CR Write-only
30 29 28 27 26 25 24
Register name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
SWRST
0
-
-
-
-
-
-
-
START
* START: Start Processing 0 = No effect 1 = Starts Manual encryption/decryption process. * SWRST: Software Reset 0 = No effect. 1 = Resets the TDES. A software triggered hardware reset of the TDES interface is performed.
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38.4.2 Name:
TDES Mode Register TDES_MR Read/Write
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10 9
CFBS
8
LOD
7
-
6 5
OPMOD
4
-
3
-
2 1
SMOD
0
-
-
-
KEYMOD
-
-
TDESMOD
CIPHER
* CIPHER: Processing Mode 0 = Decrypts data. 1 = Encrypts data. * TDESMOD: Single or Triple DES Mode 0 = Single DES processing using TDES_KEY1WxR registers. 1= Triple DES processing using TDES_KEY1WxR, TDES_KEY2WxR and TDES_KEY3WxR registers. * KEYMOD: Key Mode 0 = Three-key algorithm is selected. 1 = Two-key algorithm is selected. There is no need to write TDES_KEY3WxR registers. * SMOD: Start Mode
SMOD 0 0 0 1 Description Manual Mode. Auto Mode. PDC Mode. 1 0
* LOD = 0: The encrypted/decrypted data are available at the address specified in the receive pointer registers (TDES_RPR, TDES_RNPR). * LOD = 1: The encrypted/decrypted data are available in the output data registers.
Reserved
1
1
* OPMOD: Operation Mode
OPMOD 0 0 1 1 0 1 0 1 Description ECB: Electronic Code Book mode CBC: Cipher Block Chaining mode OFB: Output Feedback mode CFB: Cipher Feedback mode
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* LOD: Last Output Data Mode 0 = No effect. After each end of encryption/decryption, the output data is available either on the output data registers (Manual and Auto modes), or at the address specified in the receive buffer pointer (PDC mode). In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1 = The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads are necessary between consecutive encryptions/decryptions (See "Last Output Data Mode" on page 512.). Warning: In PDC mode, reading to the Output Data registers before the last data encryption/decryption process may lead to unpredictable result. * CFBS: Cipher Feedback Data Size
CFBS 0 0 1 1 0 1 0 1 Description 64-bit 32-bit 16-bit 8-bit
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38.4.3 Name:
TDES Interrupt Enable Register TDES_IER Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
URAD
0
-
-
-
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
* DATRDY: Data Ready Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable * URAD: Unspecified Register Access Detection Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
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38.4.4 Name: Access Type:
31
TDES Interrupt Disable Register TDES_IDR Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
URAD
0
-
-
-
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
* DATRDY: Data Ready Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable * URAD: Unspecified Register Access Detection Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
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38.4.5 Name:
TDES Interrupt Mask Register TDES_IMR Read-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
URAD
0
-
-
-
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
* DATRDY: Data Ready Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask * URAD: Unspecified Register Access Detection Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
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38.4.6 Name: Access Type:
31
TDES Interrupt Status Register TDES_ISR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
URAT
7 6 5 4
-
3
-
2
-
1
URAD
0
-
-
-
TXBUFE
RXBUFF
ENDTX
ENDRX
DATRDY
* DATRDY: Data Ready 0 = Output data is not valid. 1 = Encryption or decryption process is completed. DATRDY is cleared when a Manual encryption/decryption occurs (START bit in TDES_CR) or when a software triggered hardware reset of the TDES interface is performed (SWRST bit in TDES_CR). LOD = 0 (TDES_MR): In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Output Data Registers is read. In PDC mode, DATRDY is set and cleared automatically. LOD = 1 (TDES_MR): In Manual and Auto mode, the DATRDY flag can also be cleared when at least one of the Input Data Registers is written. In PDC mode, DATRDY is set and cleared automatically. * ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in TDES_RCR or TDES_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TDES_RCR or TDES_RNCR.
Note: This flag must be used only in PDC mode with LOD bit cleared.
* ENDTX: End of TX Buffer 0 = The Transmit Counter Register has not reached 0 since the last write in TDES_TCR or TDES_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TDES_TCR or TDES_TNCR.
Note: This flag must be used only in PDC mode with LOD bit set.
* RXBUFF: RX Buffer Full 0 = TDES_RCR or TDES_RNCR has a value other than 0. Note: 1 =This flag must be used only in PDC mode with LOD bit cleared. Both TDES_RCR and TDES_RNCR have a value of 0. * TXBUFE: TX Buffer Empty 0 = TDES_TCR or TDES_TNCR has a value other than 0. 1 = Both TDES_TCR and TDES_TNCR have a value of 0.
Note: This flag must be used only in PDC mode with LOD bit set.
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* URAD: Unspecified Register Access Detection Status 0 = No unspecified register access has been detected since the last SWRST. 1 = At least one unspecified register access has been detected since the last SWRST. URAD bit is reset only by the SWRST bit in the TDES_CR control register. * URAT: Unspecified Register Access Type:
URAT 0 0 1 1 0 1 0 1 Description Input Data Register written during the data processing in PDC mode. Output Data Register read during the data processing. Mode Register written during the data processing. Write-only register read access.
Only the last Unspecified Register Access Type is available through the URAT field. URAT field is reset only by the SWRST bit in the TDES_CR control register.
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38.4.7 Name: Access Type:
31
TDES Key 1 Word x Register TDES_KEY1WxR Write-only
30 29 28 27 26 25 24
KEY1Wx
23 22 21 20 19 18 17 16
KEY1Wx
15 14 13 12 11 10 9 8
KEY1Wx
7 6 5 4 3 2 1 0
KEY1Wx
* KEY1Wx: Key 1 Word x The two 32-bit Key 1 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption. KEY1W1 corresponds to the first word of the key and KEY1W2 to the last one. These registers are write-only to prevent the key from being read by another application.
38.4.8 Name:
TDES Key 2 Word x Register TDES_KEY2WxR Write-only
30 29 28 27 26 25 24
Access Type:
31
KEY2Wx
23 22 21 20 19 18 17 16
KEY2Wx
15 14 13 12 11 10 9 8
KEY2Wx
7 6 5 4 3 2 1 0
KEY2Wx
* KEY2Wx: Key 2 Word x The two 32-bit Key 2 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption. KEY2W1 corresponds to the first word of the key and KEY2W2 to the last one. These registers are write-only to prevent the key from being read by another application.
Note: KEY2WxR registers are not used in DES mode.
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38.4.9 Name:
TDES Key 3 Word x Register TDES_KEY3WxR Write-only
30 29 28 27 26 25 24
Access Type:
31
KEY3Wx
23 22 21 20 19 18 17 16
KEY3Wx
15 14 13 12 11 10 9 8
KEY3Wx
7 6 5 4 3 2 1 0
KEY3Wx
* KEY3Wx: Key 3 Word x The two 32-bit Key 3 Word Registers allow to set the 64-bit cryptographic key used for encryption/decryption. KEY3W1 corresponds to the first word of the key and KEY3W2 to the last one. These registers are write-only to prevent the key from being read by another application.
Note: KEY3WxR registers are not used in DES mode and TDES with two-key algorithm selected.
38.4.10 Name:
TDES Input Data x Register TDES_IDATAxR Write-only
30 29 28 27 26 25 24
Access Type:
31
IDATAx
23 22 21 20 19 18 17 16
IDATAx
15 14 13 12 11 10 9 8
IDATAx
7 6 5 4 3 2 1 0
IDATAx
* IDATAx: Input Data x The two 32-bit Input Data registers allow to set the 64-bit data block used for encryption/decryption. IDATA1 corresponds to the first word of the data to be encrypted/decrypted, and IDATA2 to the last one. These registers are write-only to prevent the input data from being read by another application.
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38.4.11 Name: Access Type:
31
TDES Output Data x Register TDES_ODATAxR Read-only
30 29 28 27 26 25 24
ODATAx
23 22 21 20 19 18 17 16
ODATAx
15 14 13 12 11 10 9 8
ODATAx
7 6 5 4 3 2 1 0
ODATAx
* ODATAx: Output Data x The two 32-bit Output Data registers contain the 64-bit data block which has been encrypted/decrypted. ODATA1 corresponds to the first word, ODATA2 to the last one.
38.4.12 Name:
TDES Initialization Vector x Register TDES_IVxR Write-only
30 29 28 27 26 25 24
Access Type:
31
IVx
23 22 21 20 19 18 17 16
IVx
15 14 13 12 11 10 9 8
IVx
7 6 5 4 3 2 1 0
IVx
* IVx: Initialization Vector x The two 32-bit Initialization Vector registers are used to set the 64-bit initialization vector data block, which is used by some modes of operation as an additional initial input. IV1 corresponds to the first word of the Initialization Vector, IV2 to the last one. These registers are write-only to prevent the Initialization Vector from being read by another application.
Note: These registers are not used for ECB mode and must not be written.
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39. Controller Area Network (CAN)
39.1 Description
The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/sec. CAN controller accesses are made through configuration registers. 8 independent message objects (mailboxes) are implemented. Any mailbox can be programmed as a reception buffer block (even non-consecutive buffers). For the reception of defined messages, one or several message objects can be masked without participating in the buffer feature. An interrupt is generated when the buffer is full. According to the mailbox configuration, the first message received can be locked in the CAN controller registers until the application acknowledges it, or this message can be discarded by new received messages. Any mailbox can be programmed for transmission. Several transmission mailboxes can be enabled in the same time. A priority can be defined for each mailbox independently. An internal 16-bit timer is used to stamp each received and sent message. This timer starts counting as soon as the CAN controller is enabled. This counter can be reset by the application or automatically after a reception in the last mailbox in Time Triggered Mode. The CAN controller offers optimized features to support the Time Triggered Communication (TTC) protocol.
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39.2
Block Diagram
Figure 39-1. CAN Block Diagram
Controller Area Network
CANRX CAN Protocol Controller
PIO
CANTX
Error Counter
Mailbox Priority Encoder
Control & Status MB0 MB1 MCK PMC
MBx
(x = number of mailboxes - 1)
CAN Interrupt User Interface
Internal Bus
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39.3 Application Block Diagram
Application Block Diagram
Figure 39-2.
Layers
CAN-based Profiles CAN-based Application Layer CAN Data Link Layer CAN Physical Layer
Implementation
Software Software CAN Controller Transceiver
39.4
I/O Lines Description
I/O Lines Description
Description CAN Receive Serial Data CAN Transmit Serial Data Type Input Output
Table 39-1.
Name CANRX CANTX
39.5
39.5.1
Product Dependencies
I/O Lines The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired CAN pins to their peripheral function. If I/O lines of the CAN are not used by the application, they can be used for other purposes by the PIO Controller.
39.5.2
Power Management The programmer must first enable the CAN clock in the Power Management Controller (PMC) before using the CAN. A Low-power Mode is defined for the CAN controller: If the application does not require CAN operations, the CAN clock can be stopped when not needed and be restarted later. Before stopping the clock, the CAN Controller must be in Low-power Mode to complete the current transfer. After restarting the clock, the application must disable the Low-power Mode of the CAN controller.
39.5.3
Interrupt The CAN interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the CAN interrupt requires the AIC to be programmed first. Note that it is not recommended to use the CAN interrupt line in edge-sensitive mode.
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39.6
39.6.1
CAN Controller Features
CAN Protocol Overview The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s. The CAN protocol supports four different frame types: * Data frames: They carry data from a transmitter node to the receiver nodes. The overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame. * Remote frames: A destination node can request data from the source by sending a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node then sends a data frame as a response to this node request. * Error frames: An error frame is generated by any node that detects a bus error. * Overload frames: They provide an extra delay between the preceding and the successive data frames or remote frames. The Atmel CAN controller provides the CPU with full functionality of the CAN protocol V2.0 Part A and V2.0 Part B. It minimizes the CPU load in communication overhead. The Data Link Layer and part of the physical layer are automatically handled by the CAN controller itself. The CPU reads or writes data or messages via the CAN controller mailboxes. An identifier is assigned to each mailbox. The CAN controller encapsulates or decodes data messages to build or to decode bus data frames. Remote frames, error frames and overload frames are automatically handled by the CAN controller under supervision of the software application.
39.6.2
Mailbox Organization The CAN module has 8 buffers, also called channels or mailboxes. An identifier that corresponds to the CAN identifier is defined for each active mailbox. Message identifiers can match the standard frame identifier or the extended frame identifier. This identifier is defined for the first time during the CAN initialization, but can be dynamically reconfigured later so that the mailbox can handle a new message family. Several mailboxes can be configured with the same ID. Each mailbox can be configured in receive or in transmit mode independently. The mailbox object type is defined in the MOT field of the CAN_MMRx register.
39.6.2.1
Message Acceptance Procedure If the MIDE field in the CAN_MIDx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier. Once a new message is received, its ID is masked with the CAN_MAMx value and compared with the CAN_MIDx value. If accepted, the message ID is copied to the CAN_MIDx register.
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Figure 39-3. Message Acceptance Procedure
CAN_MIDx CAN_MAMx Message Received
&
&
==
Yes Message Accepted
No
Message Refused
CAN_MFIDx
If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx. To speed up the decoding, masked bits are grouped in the family ID register (CAN_MFIDx). For example, if the following message IDs are handled by the same mailbox:
ID0 000011101000100100010010000100 0 11 00b ID1 000011101000100100010010000100 0 11 01b ID2 000011101000100100010010000100 0 11 10b ID3 000011101000100100010010000100 0 11 11b ID4 000011101000100100010010000100 1 11 00b ID5 000011101000100100010010000100 1 11 01b ID6 000011101000100100010010000100 1 11 10b ID7 000011101000100100010010000100 1 11 11b
The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values:
CAN_MIDx = 000011101000100100010010000100 x 11 xxb CAN_MAMx = 111111111111111111111111111111 0 11 00b
If Mailbox x receives a message with ID6, then CAN_MIDx and CAN_MFIDx are set:
CAN_MIDx = 000011101000100100010010000100 1 11 10b CAN_MFIDx = 00000000000000000000000000000000110b
If the application associates a handler for each message ID, it may define an array of pointers to functions:
void (*pHandler[8])(void);
When a message is received, the corresponding handler can be invoked using CAN_MFIDx register and there is no need to check masked bits:
unsigned int MFID0_register; MFID0_register = Get_CAN_MFID0_Register(); // Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register pHandler[MFID0_register]();
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39.6.2.2 Receive Mailbox When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is found, then the message is stored in its data registers. Depending on the configuration, the mailbox is disabled as long as the message has not been acknowledged by the application (Receive only), or, if new messages with the same ID are received, then they overwrite the previous ones (Receive with overwrite). It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers. Several mailboxes can be chained to receive a buffer. They must be configured with the same ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite Mode. The last mailbox can be used to detect a buffer overflow.
Mailbox Object Type Receive Description The first message received is stored in mailbox data registers. Data remain available until the next transfer request. The last message received is stored in mailbox data register. The next message always overwrites the previous one. The application has to check whether a new message has not overwritten the current one while reading the data registers. A remote frame is sent by the mailbox. The answer received is stored in mailbox data register. This extends Receive mailbox features. Data remain available until the next transfer request.
Receive with overwrite
Consumer
39.6.2.3
Transmit Mailbox When transmitting a message, the message length and data are written to the transmit mailbox with the correct identifier. For each transmit mailbox, a priority is assigned. The controller automatically sends the message with the highest priority first (set with the field PRIOR in CAN_MMRx register). It is also possible to configure a mailbox in Producer Mode. In this mode, when a remote frame is received, the mailbox data are sent automatically. By enabling this mode, a producer can be done using only one mailbox instead of two: one to detect the remote frame and one to send the answer.
Mailbox Object Type Transmit
Description The message stored in the mailbox data registers will try to win the bus arbitration immediately or later according to or not the Time Management Unit configuration (see Section 39.6.3). The application is notified that the message has been sent or aborted. The message prepared in the mailbox data registers will be sent after receiving the next remote frame. This extends transmit mailbox features.
Producer
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39.6.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register). It is automatically cleared in the following cases: * after a reset * when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and SLEEP bit set in the CAN_SR) * after a reset of the CAN controller (CANEN bit in the CAN_MR register) * in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the MRDY signal in the CAN_MSRlast_mailbox_number register). The application can also reset the internal timer by setting TIMRST in the CAN_TCR register. The current value of the internal timer is always accessible by reading the CAN_TIM register. When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR register is set. TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated while TOVF is set. In a CAN network, some CAN devices may have a larger counter. In this case, the application can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device. This feature is enabled by setting TIMFRZ in the CAN_MR register. The CAN_TIM register is frozen to the FFFFh value. A clear condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered. To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register after each start of frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR register is set, the value is captured at each End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the CAN_SR register. The time management unit can operate in one of the two following modes: * Timestamping mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame * Time Triggered mode: A mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. Timestamping Mode is enabled by clearing TTM field in the CAN_MR register. Time Triggered Mode is enabled by setting TTM field in the CAN_MR register.
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39.6.4 39.6.4.1 CAN 2.0 Standard Features CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments. The CAN protocol specification partitions the nominal bit time into four different segments: Figure 39-4. Partition of the CAN Bit Time
NOMINAL BIT TIME
SYNC_SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
Sample Point
TIME QUANTUM: The TIME QUANTUM is a fixed unit of time derived from the MCK period. The total number of TIME QUANTA in a bit time is programmable from 8 to 25. SYNC SEG: This part of the bit time is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment. PROP SEG: This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal's propagation time on the bus line, the input comparator delay, and the output driver delay. This parameter is defined in the PROPAG field of the CAN_BR register. PHASE SEG1, PHASE SEG2: The Phase-Buffer-Segments are used to compensate for edge phase errors. These segments can be lengthened or shortened by resynchronization. These parameters are defined in the PHASE1 and PHASE2 fields of the CAN_BR register. SAMPLE POINT: The SAMPLE POINT is the point in time at which the bus level is read and interpreted as the value of that respective bit. Its location is at the end of PHASE_SEG1. If the SMP field in the CAN_BR register is set, then the incoming bit stream is sampled three times with a period of half a CAN clock period, centered on sample point. In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP, PROPAG, PHASE1 and PHASE2). t BIT = t CSC + t PRS + t PHS1 + t PHS2 The time quantum is calculated as follows: t CSC = ( BRP + 1 ) MCK
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t PRS = t CSC x ( PROPAG + 1 ) t PHS1 = t CSC x ( PHASE1 + 1 ) t PHS2 = t CSC x ( PHASE2 + 1 ) To compensate for phase shifts between clock oscillators of different controllers on the bus, the CAN controller must resynchronize on any revelant signal edge of the current transmission. The resynchronization shortenes or lengthenes the bit time such that the position of the sample point is shifted with regard to the detected edge. The resynchronization jump width (SJW) defines the maximum of time by which a bit period may be shortened or lengthened by resynchronization. t SJW = t CSC x ( SJW + 1 ) Figure 39-5. CAN Bit Timing
MCK
CAN Clock tCSC tPRS tPHS1 tPHS2
NOMINAL BIT TIME
SYNC_ SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
Sample Point
Transmission Point
Example of bit timing determination for CAN baudrate of 500 Kbit/s:
MCK = 48MHz CAN baudrate= 500kbit/s => bit time= 2us Delay of the bus driver: 50 ns Delay of the receiver: 30ns Delay of the bus line (20m): 110ns The total number of time quanta in a bit time must be comprised between 8 and 25. If we fix the bit time to 16 time quanta: Tcsc = 1 time quanta = bit time / 16 = 125 ns => BRP = (Tcsc x MCK) - 1 = 5 The propagation segment time is equal to twice the sum of the signal's propagation time on the bus line, the receiver delay and the output driver delay: Tprs = 2 * (50+30+110) ns = 380 ns = 3 Tcsc => PROPAG = Tprs/Tcsc - 1 = 2 The remaining time for the two phase segments is: Tphs1 + Tphs2 = bit time - Tcsc - Tprs = (16 - 1 - 3)Tcsc Tphs1 + Tphs2 = 12 Tcsc
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Because this number is even, we choose Tphs2 = Tphs1 (else we would choose Tphs2 = Tphs1 + Tcsc) Tphs1 = Tphs2 = (12/2) Tcsc = 6 Tcsc => PHASE1 = PHASE2 = Tphs1/Tcsc - 1 = 5 The resynchronization jump width must be comprised between 1 Tcsc and the minimum of 4 Tcsc and Tphs1. We choose its maximum value: Tsjw = Min(4 Tcsc,Tphs1) = 4 Tcsc => SJW = Tsjw/Tcsc - 1 = 3 Finally: CAN_BR = 0x0053255
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CAN Bus Synchronization Two types of synchronization are distinguished: "hard synchronization" at the start of a frame and "resynchronization" inside a frame. After a hard synchronization, the bit time is restarted with the end of the SYNC_SEG segment, regardless of the phase error. Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge. The effect of resynchronization is the same as that of hard synchronization when the magnitude of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width (tSJW). When the magnitude of the phase error is larger than the resynchronization jump width and * the phase error is positive, then PHASE_SEG1 is lengthened by an amount equal to the resynchronization jump width. * the phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the resynchronization jump width. Figure 39-6. CAN Resynchronization
THE PHASE ERROR IS POSITIVE (the transmitter is slower than the receiver) Received data bit Nominal Sample point Sample point after resynchronization
Nominal bit time (before resynchronization)
SYNC_ SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
SYNC_ SEG
Phase error Bit time with resynchronization
Phase error (max Tsjw)
SYNC_ SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
SYNC_ SEG
THE PHASE ERROR IS NEGATIVE (the transmitter is faster than the receiver) Received data bit
Sample point after resynchronization
Nominal Sample point
Nominal bit time (before resynchronization)
PHASE_SEG2
SYNC_ SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
SYNC_ SEG
Phase error
Bit time with resynchronization
PHASE_ SYNC_ SEG2 SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
SYNC_ SEG
Phase error (max Tsjw)
Autobaud Mode The autobaud feature is enabled by setting the ABM field in the CAN_MR register. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It can not send any message. The errors flags are updated. The bit timing can be adjusted until no error occurs (good configuration found). In this mode, the error counters are
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frozen. To go back to the standard mode, the ABM bit must be cleared in the CAN_MR register. 39.6.4.2 Error Detection There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their correspondence): * CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame. * Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting with the next bit-time. * Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. An error frame is generated and starts with the next bit time. * Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in one of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error has occurred and an error frame is generated. * Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. If this is the case, at least one other node has received the frame correctly. If not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an Error Frame transmission. Fault Confinement To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The counters are incremented upon detected errors and respectively are decremented upon correct transmissions or receptions. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags. The controller changes to the Error Passive state if there is an accumulation of errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state transition to Bus Off.
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Figure 39-7. Line Error Mode
Init
TEC > 127 or REC > 127
ERROR ACTIVE
128 occurences of 11 consecutive recessive bits or CAN controller reset
ERROR PASSIVE
TEC < 127 and REC < 127
BUS OFF
TEC > 255
An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via the CAN_ECR register. The state of the CAN controller is automatically updated according to these counter values. If the CAN controller is in Error Active state, then the ERRA bit is set in the CAN_SR register. The corresponding interrupt is pending while the interrupt is not masked in the CAN_IMR register. If the CAN controller is in Error Passive Mode, then the ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is set in the CAN_IMR register. If the CAN is in Bus-off Mode, then the BOFF bit is set in the CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in the CAN_IMR register. When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the interrupt is set in the CAN_IMR register. Refer to the Bosch CAN specification v2.0 for details on fault confinement. 39.6.4.3 Overload The overload frame is provided to request a delay of the next data or remote frame by the receiver node ("Request overload frame") or to signal certain error conditions ("Reactive overload frame") related to the intermission field respectively. Reactive overload frames are transmitted after detection of the following error conditions: * Detection of a dominant bit during the first two bits of the intermission field * Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR register.
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Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR register is not set. An overload flag is generated in the same way as an error flag, but error counters do not increment. 39.6.5 Low-power Mode In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive. In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP signal in the CAN_SR register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Lowpower Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detection of 11 consecutive recessive bits on the bus. 39.6.5.1 Enabling Low-power Mode A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent. When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The WAKEUP signal is automatically cleared once SLEEP is set. Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those messages with higher priority than the last message transmitted can be received between the LPM command and entry in Low-power Mode. Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip's Power Management Controller (PMC). The CAN controller drains only the static current. Error counters are disabled while the SLEEP signal is set to one. Thus, to enter Low-power Mode, the software application must: - Set LPM field in the CAN_MR register - Wait for SLEEP signal rising Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC).
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Figure 39-8. Enabling Low-power Mode
Arbitration lost
CAN BUS LPEN= 1 LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSR1) MRDY (CAN_MSR3) CAN_TIM
Mailbox 1
Mailbox 3
0x0
39.6.5.2
Disabling Low-power Mode The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power Mode by programming the CAN controller. To disable Low-power Mode, the software application must: - Enable the CAN Controller clock. This is done by programming the Power Management Controller (PMC). - Clear the LPM field in the CAN_MR register The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive "recessive" bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while WAKEUP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set. If no message is being sent on the bus, then the CAN controller is able to send a message eleven bit times after disabling Low-power Mode. If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized with the bus activity in the next interframe. The previous message is lost (see Figure 39-9).
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Figure 39-9. Disabling Low-power Mode
Bus Activity Detected Message x Interframe synchronization
CAN BUS LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR)
Message lost
MRDY (CAN_MSRx)
39.7
39.7.1
Functional Description
CAN Controller Initialization After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC). The CAN controller must be initialized with the CAN network parameters. The CAN_BR register defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller is enabled by setting the CANEN field in the CAN_MR register. The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage, the internal CAN controller state machine is reset, error counters are reset to 0, error flags are reset to 0. Once the CAN controller is enabled, bus synchronization is done automatically by scanning eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset). The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags, the CAN_BR register values synchronized with the network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register.
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Figure 39-10. Possible Initialization Procedure
Enable CAN Controller Clock (PMC) Enable CAN Controller Interrupt Line (AIC)
Configure a Mailbox in Reception Mode
Change CAN_BR value (ABM == 1 and CANEN == 1)
Errors ? (CAN_SR or CAN_MSRx)
Yes
No ABM = 0 and CANEN = 0
CANEN = 1 (ABM == 0)
End of Initialization
39.7.2
CAN Controller Interrupt Handling There are two different types of interrupts. One type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources. All interrupt sources can be masked by writing the corresponding field in the CAN_IDR register. They can be unmasked by writing to the CAN_IER register. After a power-up reset, all interrupt sources are disabled (masked). The current mask status can be checked by reading the CAN_IMR register. The CAN_SR register gives all interrupt source states. The following events may initiate one of the two interrupts: * Message object interrupt - Data registers in the mailbox object are available to the application. In Receive Mode, a new message was received. In Transmit Mode, a message was transmitted successfully. - A sent transmission was aborted. * System interrupts - Bus-off interrupt: The CAN module enters the bus-off state. - Error-passive interrupt: The CAN module enters Error Passive Mode. - Error-active Mode: The CAN module is neither in Error Passive Mode nor in Busoff mode. 545
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- Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter value exceeds 96. - Wake-up interrupt: This interrupt is generated after a wake-up and a bus synchronization. - Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all pending messages in transmission have been sent. - Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over. - Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register. All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the CAN_SR register.
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39.7.3 39.7.3.1 CAN Controller Message Handling Receive Handling Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is stored in the mailbox.
Simple Receive Mailbox A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance Mask must be set before the Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. Message data are stored in the mailbox data register until the software application notifies that data processing has ended. This is done by asking for a new transfer command, setting the MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal. The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx register. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while MRDY flag is set in the CAN_MSRx register. See Figure 39-11. Figure 39-11. Receive Mailbox
Message ID = CAN_MIDx
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx)
Message 1
Message 2 lost
Message 3
(CAN_MDLx CAN_MDHx) MTCR (CAN_MCRx)
Message 1
Message 3
Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx
Note:
In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler instruction.
Receive with Overwrite Mailbox
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A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register. If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx register notifies the software that a message has been dropped by the mailbox. This flag is cleared when reading the CAN_MSRx register. The CAN controller may store a new message in the CAN data registers while the application reads them. To check that CAN_MDHx and CAN_MDLx do not belong to different messages, the application must check the MMI field in the CAN_MSRx register before and after reading CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data registers have been read, the software application has to re-read CAN_MDHx and CAN_MDLx (see Figure 39-12). Figure 39-12. Receive with Overwrite Mailbox
Message ID = CAN_MIDx
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) (CAN_MDLx CAN_MDHx) MTCR (CAN_MCRx)
Message 1
Message 2
Message 3
Message 4
Message 1
Message 2
Message 3
Message 4
Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx
Chaining Mailboxes Several mailboxes may be used to receive a buffer split into several messages with the same ID. In this case, the mailbox with the lowest number is serviced first. In the receive and receive with overwrite modes, the field PRIOR in the CAN_MMRx register has no effect. If Mailbox 0 and Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0 and the second message is received by Mailbox 5. Mailbox 0 must be configured in Receive Mode (i.e., the first message received is considered) and Mailbox 5 must be configured in Receive with Overwrite Mode. Mailbox 0 cannot be configured in Receive with Overwrite Mode; otherwise, all messages are accepted by this mailbox and Mailbox 5 is never serviced.
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If several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in Receive Mode. The first message received is handled by the first mailbox, the second one is refused by the first mailbox and accepted by the second mailbox, the last message is accepted by the last mailbox and refused by previous ones (see Figure 39-13). Figure 39-13. Chaining Three Mailboxes to Receive a Buffer Split into Three Messages
Buffer split in 3 messages
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz)
Message s1
Message s2
Message s3
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR
If the number of mailboxes is not sufficient (the MMI flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see Figure 39-14).
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Figure 39-14. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages
Buffer split in 4 messages
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz)
Message s1
Message s2
Message s3
Message s4
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR
39.7.3.2
Transmission Handling A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers. The message is sent once the software asks for a transfer command setting the MTCR bit and the message data length in the CAN_MCRx register. The MRDY flag remains at zero as long as the message has not been sent or aborted. It is important to note that no access to the mailbox data register is allowed while the MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field. The answer to the remote frame is handled by another reception mailbox. In this case, the device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote frame emission and the answer reception using only one mailbox configured in Consumer Mode. Refer to the section "Remote Frame Handling" on page 551. Several messages can try to win the bus arbitration in the same time. The message with the highest priority is sent first. Several transfer request commands can be generated at the same time by setting MBx bits in the CAN_TCR register. The priority is set in the PRIOR field of the CAN_MMRx register. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox
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0 and mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first. Setting the MACR bit in the CAN_MCRx register aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR register. If the message is being sent when the abort command is set, then the application is notified by the MRDY bit set and not the MABT in the CAN_MSRx register. Otherwise, if the message has not been sent, then the MRDY and the MABT are set in the CAN_MSR register. When the bus arbitration is lost by a mailbox message, the CAN controller tries to win the next bus arbitration with the same message if this one still has the highest priority. Messages to be sent are re-tried automatically until they win the bus arbitration. This feature can be disabled by setting the bit DRPT in the CAN_MR register. In this case if the message was not sent the first time it was transmitted to the CAN transceiver, it is automatically aborted. The MABT flag is set in the CAN_MSRx register until the next transfer command. Figure 39-15 shows three MBx message attempts being made (MRDY of MBx set to 0). The first MBx message is sent, the second is aborted and the last one is trying to be aborted but too late because it has already been transmitted to the CAN transceiver. Figure 39-15. Transmitting Messages
CAN BUS MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Reading CAN_MSRx Writing CAN_MDHx & CAN_MDLx Abort MBx message Try to Abort MBx message MBx message MBx message
39.7.3.3
Remote Frame Handling Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages.
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Figure 39-16. Producer / Consumer Model
Producer
Request
PUSH MODEL
CAN Data Frame
Consumer
Indication(s)
PULL MODEL
Producer
Indications CAN Remote Frame
Consumer
Request(s)
Response
CAN Data Frame Confirmation(s)
In Pull Mode, a consumer transmits a remote frame to the producer. When the producer receives a remote frame, it sends the answer accepted by one or many consumers. Using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in Transmit Mode to send remote frames, and at least one in Receive Mode to capture the producer's answer. The same structure is applicable to a producer: one reception mailbox is required to get the remote frame and one transmit mailbox to answer. Mailboxes can be configured in Producer or Consumer Mode. A lonely mailbox can handle the remote frame and the answer. With 8 mailboxes, the CAN controller can handle 8 independent producers/consumers. Producer Configuration A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx register. Data is sent after the reception of a remote frame as soon as it wins the bus arbitration. The MRDY flag remains at zero as long as the message has not been sent or aborted. No access to the mailbox data register can be done while MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. If a remote frame is received while no data are ready to be sent (signal MRDY set in the CAN_MSRx register), then the MMI signal is set in the CAN_MSRx register. This bit is cleared by reading the CAN_MSRx register. The MRTR field in the CAN_MSRx register has no meaning. This field is used only when using Receive and Receive with Overwrite modes.
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After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message may be aborted by setting the MACR bit in the CAN_MCR register. Please refer to the section "Transmission Handling" on page 550. Figure 39-17. Producer Handling
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) Reading CAN_MSRx Remote Frame Message 1 Remote Frame Remote Frame Message 2
(CAN_MDLx CAN_MDHx)
Message 1
Message 2
Consumer Configuration A mailbox is in Consumer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Consumer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first transfer request command. The software application sends a remote frame by setting the MTCR bit in the CAN_MCRx register or the MBx bit in the global CAN_TCR register. The application is notified of the answer by the MRDY flag set in the CAN_MSRx register. The application can read the data contents in the CAN_MDHx and CAN_MDLx registers. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. The MRTR bit in the CAN_MCRx register has no effect. This field is used only when using Transmit Mode. After a remote frame has been sent, the consumer mailbox functions as a reception mailbox. The first message received is stored in the mailbox data registers. If other messages intended for this mailbox have been sent while the MRDY flag is set in the CAN_MSRx register, they will be lost. The application is notified by reading the MMI field in the CAN_MSRx register. The read operation automatically clears the MMI flag. If several messages are answered by the Producer, the CAN controller may have one mailbox in consumer configuration, zero or several mailboxes in Receive Mode and one mailbox in Receive with Overwrite Mode. In this case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR register.
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Figure 39-18. Consumer Handling
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) Remote Frame Message x Remote Frame Message y
(CAN_MDLx CAN_MDHx)
Message x
Message y
39.7.4
CAN Controller Timing Modes Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes: * Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame. * Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR register. Time Triggered Mode is enabled by setting the TTM bit in the CAN_MR register.
39.7.4.1
Timestamping Mode Each mailbox has its own timestamp value. Each time a message is sent or received by a mailbox, the 16-bit value MTIMESTAMP of the CAN_TIMESTP register is transferred to the LSB bits of the CAN_MSRx register. The value read in the CAN_MSRx register corresponds to the internal timer value at the Start Of Frame or the End Of Frame of the message handled by the mailbox.
Figure 39-19. Mailbox Timestamp
Start of Frame End of Frame
CAN BUS CAN_TIM
Message 1
Message 2
TEOF (CAN_MR) TIMESTAMP (CAN_TSTP) MTIMESTAMP (CAN_MSRx) MTIMESTAMP (CAN_MSRy) Timestamp 1 Timestamp 2
Timestamp 1 Timestamp 2
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39.7.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window.
Figure 39-20. Time Triggered Principle
Time Cycle Reference Message Reference Message
Time Windows for Messages Global Time
Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Triggered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at 0. Synchronization by a Reference Message In Time Triggered Mode, the internal timer counter is automatically reset when a new message is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the rising edge of the MRDY signal in the CAN_MSRx register. This allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window. Transmitting within a Time Window A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared with each mailbox time mark. When the internal timer counter reaches the MTIMEMARK value, an internal timer event for the mailbox is generated for the mailbox. In Time Triggered Mode, transmit operations are delayed until the internal timer event for the mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx register. The message is not sent until the CAN_TIM value is less than the MTIMEMARK value defined in the CAN_MMRx register. If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until the next internal time trigger event. This prevents overlapping the next time window, but the message is still pending and is retried in the next time window when CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting the DRPT field in the CAN_MR register. Freezing the Internal Timer Counter The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter
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is frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set. Figure 39-21. Time Triggered Operations
End of Frame Message x Arbitration Lost Message y Arbitration Win
CAN BUS
Reference Message
Message y Internal Counter Reset
CAN_TIM Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MRDY (CAN_MSRx) MTIMEMARKy == CAN_TIM MTIMEMARKx == CAN_TIM
Timer Event y MRDY (CAN_MSRy)
Time Window Basic Cycle
End of Frame
Message x Arbitration Win Message x
CAN BUS CAN_TIM
Reference Message
Internal Counter Reset
Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MRDY (CAN_MSRx) Time Window Basic Cycle MTIMEMARKx == CAN_TIM
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39.8 Controller Area Network (CAN) User Interface
CAN Memory Map
Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Baudrate Register Timer Register Timestamp Register Error Counter Register Transfer Command Register Abort Command Register Reserved Mailbox 0 Mode Register Mailbox 0 Acceptance Mask Register Mailbox 0 ID Register Mailbox 0 Family ID Register Mailbox 0 Status Register Mailbox 0 Data Low Register Mailbox 0 Data High Register Mailbox 0 Control Register Mailbox 1 Mode Register Mailbox 1 Acceptance Mask Register Mailbox 1 ID register Mailbox 1 Family ID Register Mailbox 1 Status Register Mailbox 1 Data Low Register Mailbox 1 Data High Register Mailbox 1 Control Register ... Name CAN_MR CAN_IER CAN_IDR CAN_IMR CAN_SR CAN_BR CAN_TIM CAN_TIMESTP CAN_ECR CAN_TCR CAN_ACR - CAN_MMR0 CAN_MAM0 CAN_MID0 CAN_MFID0 CAN_MSR0 CAN_MDL0 CAN_MDH0 CAN_MCR0 CAN_MMR1 CAN_MAM1 CAN_MID1 CAN_MFID1 CAN_MSR1 CAN_MDL1 CAN_MDH1 CAN_MCR1 ... Access Read-Write Write-only Write-only Read-only Read-only Read/Write Read-only Read-only Read-only Write-only Write-only - Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read/Write Write-only Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read/Write Write-only ... Reset State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -
Table 39-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028
0x0100 - 0x01FC 0x0200 0x0204 0x0208 0x020C 0x0210 0x0214 0x0218 0x021C 0x0220 0x0224 0x0228 0x022C 0x0230 0x0234 0x0238 0x023C ...
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39.8.1 Name: Access Type:
31 - 23 - 15 - 7 DRPT
CAN Mode Register CAN_MR Read/Write
30 - 22 - 14 - 6 TIMFRZ 29 - 21 - 13 - 5 TTM 28 - 20 - 12 - 4 TEOF 27 - 19 - 11 - 3 OVL 26 25 24
18 - 10 - 2 ABM
17 - 9 - 1 LPM
16 - 8 - 0 CANEN
* CANEN: CAN Controller Enable 0 = The CAN Controller is disabled. 1 = The CAN Controller is enabled. * LPM: Disable/Enable Low Power Mode w Power Mode. 1 = Enable Low Power M CAN controller enters Low Power Mode once all pending messages have been transmitted. * ABM: Disable/Enable Autobaud/Listen mode 0 = Disable Autobaud/listen mode. 1 = Enable Autobaud/listen mode. * OVL: Disable/Enable Overload Frame 0 = No overload frame is generated. 1 = An overload frame is generated after each successful reception for mailboxes configured in Receive with/without overwrite Mode, Producer and Consumer. * TEOF: Timestamp messages at each end of Frame 0 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame. 1 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame. * TTM: Disable/Enable Time Triggered Mode 0 = Time Triggered Mode is disabled. 1 = Time Triggered Mode is enabled. * TIMFRZ: Enable Timer Freeze 0 = The internal timer continues to be incremented after it reached 0xFFFF. 1 = The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See "Freezing the Internal Timer Counter" on page 555. * DRPT: Disable Repeat 0 = When a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1 = When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.
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39.8.2 Name: Access Type:
31 - 23 TSTP 15 - 7 MB7
CAN Interrupt Enable Register CAN_IER Write-only
30 - 22 TOVF 14 - 6 MB6 29 - 21 WAKEUP 13 - 5 MB5 28 BERR 20 SLEEP 12 - 4 MB4 27 FERR 19 BOFF 11 - 3 MB3 26 AERR 18 ERRP 10 - 2 MB2 25 SERR 17 WARN 9 - 1 MB1 24 CERR 16 ERRA 8 - 0 MB0
* MBx: Mailbox x Interrupt Enable 0 = No effect. 1 = Enable Mailbox x interrupt. * ERRA: Error Active mode Interrupt Enable 0 = No effect. 1 = Enable ERRA interrupt. * WARN: Warning Limit Interrupt Enable 0 = No effect. 1 = Enable WARN interrupt. * ERRP: Error Passive mode Interrupt Enable 0 = No effect. 1 = Enable ERRP interrupt. * BOFF: Bus-off mode Interrupt Enable 0 = No effect. 1 = Enable BOFF interrupt. * SLEEP: Sleep Interrupt Enable 0 = No effect. 1 = Enable SLEEP interrupt. * WAKEUP: Wakeup Interrupt Enable 0 = No effect. 1 = Enable SLEEP interrupt. * TOVF: Timer Overflow Interrupt Enable 0 = No effect. 1 = Enable TOVF interrupt. * TSTP: TimeStamp Interrupt Enable 0 = No effect. 1 = Enable TSTP interrupt. * CERR: CRC Error Interrupt Enable 0 = No effect. 1 = Enable CRC Error interrupt. 559
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* SERR: Stuffing Error Interrupt Enable 0 = No effect. 1 = Enable Stuffing Error interrupt. * AERR: Acknowledgment Error Interrupt Enable 0 = No effect. 1 = Enable Acknowledgment Error interrupt. * FERR: Form Error Interrupt Enable 0 = No effect. 1 = Enable Form Error interrupt. * BERR: Bit Error Interrupt Enable 0 = No effect. 1 = Enable Bit Error interrupt.
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39.8.3 Name: Access Type:
31 - 23 TSTP 15 - 7 MB7
CAN Interrupt Disable Register CAN_IDR Write-only
30 - 22 TOVF 14 - 6 MB6 29 - 21 WAKEUP 13 - 5 MB5 28 BERR 20 SLEEP 12 - 4 MB4 27 FERR 19 BOFF 11 - 3 MB3 26 AERR 18 ERRP 10 - 2 MB2 25 SERR 17 WARN 9 - 1 MB1 24 CERR 16 ERRA 8 - 0 MB0
* MBx: Mailbox x Interrupt Disable 0 = No effect. 1 = Disable Mailbox x interrupt. * ERRA: Error Active Mode Interrupt Disable 0 = No effect. 1 = Disable ERRA interrupt. * WARN: Warning Limit Interrupt Disable 0 = No effect. 1 = Disable WARN interrupt. * ERRP: Error Passive mode Interrupt Disable 0 = No effect. 1 = Disable ERRP interrupt. * BOFF: Bus-off mode Interrupt Disable 0 = No effect. 1 = Disable BOFF interrupt. * SLEEP: Sleep Interrupt Disable 0 = No effect. 1 = Disable SLEEP interrupt. * WAKEUP: Wakeup Interrupt Disable 0 = No effect. 1 = Disable WAKEUP interrupt. * TOVF: Timer Overflow Interrupt 0 = No effect. 1 = Disable TOVF interrupt. * TSTP: TimeStamp Interrupt Disable 0 = No effect. 1 = Disable TSTP interrupt. * CERR: CRC Error Interrupt Disable 0 = No effect. 1 = Disable CRC Error interrupt. 561
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* SERR: Stuffing Error Interrupt Disable 0 = No effect. 1 = Disable Stuffing Error interrupt. * AERR: Acknowledgment Error Interrupt Disable 0 = No effect. 1 = Disable Acknowledgment Error interrupt. * FERR: Form Error Interrupt Disable 0 = No effect. 1 = Disable Form Error interrupt. * BERR: Bit Error Interrupt Disable 0 = No effect. 1 = Disable Bit Error interrupt.
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39.8.4 Name: Access Type:
31 - 23 TSTP 15 - 7 MB7
CAN Interrupt Mask Register CAN_IMR Read-only
30 - 22 TOVF 14 - 6 MB6 29 - 21 WAKEUP 13 - 5 MB5 28 BERR 20 SLEEP 12 - 4 MB4 27 FERR 19 BOFF 11 - 3 MB3 26 AERR 18 ERRP 10 - 2 MB2 25 SERR 17 WARN 9 - 1 MB1 24 CERR 16 ERRA 8 - 0 MB0
* MBx: Mailbox x Interrupt Mask 0 = Mailbox x interrupt is disabled. 1 = Mailbox x interrupt is enabled. * ERRA: Error Active mode Interrupt Mask 0 = ERRA interrupt is disabled. 1 = ERRA interrupt is enabled. * WARN: Warning Limit Interrupt Mask 0 = Warning Limit interrupt is disabled. 1 = Warning Limit interrupt is enabled. * ERRP: Error Passive Mode Interrupt Mask 0 = ERRP interrupt is disabled. 1 = ERRP interrupt is enabled. * BOFF: Bus-off Mode Interrupt Mask 0 = BOFF interrupt is disabled. 1 = BOFF interrupt is enabled. * SLEEP: Sleep Interrupt Mask 0 = SLEEP interrupt is disabled. 1 = SLEEP interrupt is enabled. * WAKEUP: Wakeup Interrupt Mask 0 = WAKEUP interrupt is disabled. 1 = WAKEUP interrupt is enabled. * TOVF: Timer Overflow Interrupt Mask 0 = TOVF interrupt is disabled. 1 = TOVF interrupt is enabled. * TSTP: Timestamp Interrupt Mask 0 = TSTP interrupt is disabled. 1 = TSTP interrupt is enabled. * CERR: CRC Error Interrupt Mask 0 = CRC Error interrupt is disabled. 1 = CRC Error interrupt is enabled. 563
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* SERR: Stuffing Error Interrupt Mask 0 = Bit Stuffing Error interrupt is disabled. 1 = Bit Stuffing Error interrupt is enabled. * AERR: Acknowledgment Error Interrupt Mask 0 = Acknowledgment Error interrupt is disabled. 1 = Acknowledgment Error interrupt is enabled. * FERR: Form Error Interrupt Mask 0 = Form Error interrupt is disabled. 1 = Form Error interrupt is enabled. * BERR: Bit Error Interrupt Mask 0 = Bit Error interrupt is disabled. 1 = Bit Error interrupt is enabled.
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39.8.5 Name: Access Type:
31 OVLSY 23 TSTP 15 - 7 MB7
CAN Status Register CAN_SR Read-only
30 TBSY 22 TOVF 14 - 6 MB6 29 RBSY 21 WAKEUP 13 - 5 MB5 28 BERR 20 SLEEP 12 - 4 MB4 27 FERR 19 BOFF 11 - 3 MB3 26 AERR 18 ERRP 10 - 2 MB2 25 SERR 17 WARN 9 - 1 MB1 24 CERR 16 ERRA 8 - 0 MB0
* MBx: Mailbox x Event 0 = No event occurred on Mailbox x. 1 = An event occurred on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx register. * ERRA: Error Active mode 0 = CAN controller is not in error active mode 1 = CAN controller is in error active mode This flag is set depending on TEC and REC counter values. It is set when node is neither in error passive mode nor in bus off mode. This flag is automatically reset when above condition is not satisfied. * WARN: Warning Limit 0 = CAN controller Warning Limit is not reached. 1 = CAN controller Warning Limit is reached. This flag is set depending on TEC and REC counters values. It is set when at least one of the counters values exceeds 96. This flag is automatically reset when above condition is not satisfied. * ERRP: Error Passive mode 0 = CAN controller is not in error passive mode 1 = CAN controller is in error passive mode This flag is set depending on TEC and REC counters values. A node is error passive when TEC counter is greater or equal to 128 (decimal) or when the REC counter is greater or equal to 128 (decimal) and less than 256. This flag is automatically reset when above condition is not satisfied. * BOFF: Bus Off mode 0 = CAN controller is not in bus-off mode 1 = CAN controller is in bus-off mode This flag is set depending on TEC counter value. A node is bus off when TEC counter is greater or equal to 256 (decimal). This flag is automatically reset when above condition is not satisfied. * SLEEP: CAN controller in Low power Mode 0 = CAN controller is not in low power mode. 1 = CAN controller is in low power mode.
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This flag is automatically reset when Low power mode is disabled * WAKEUP: CAN controller is not in Low power Mode 0 = CAN controller is in low power mode. 1 = CAN controller is not in low power mode. When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the CAN Controller enters Low Power mode. * TOVF: Timer Overflow 0 = The timer has not rolled-over FFFFh to 0000h. 1 = The timer rolls-over FFFFh to 0000h. This flag is automatically cleared by reading CAN_SR register. * TSTP Timestamp 0 = No bus activity has been detected. 1 = A start of frame or an end of frame has been detected (according to the TEOF field in the CAN_MR register). This flag is automatically cleared by reading the CAN_SR register. * CERR: Mailbox CRC Error 0 = No CRC error occurred during a previous transfer. 1 = A CRC error occurred during a previous transfer. A CRC error has been detected during last reception. This flag is automatically cleared by reading CAN_SR register. * SERR: Mailbox Stuffing Error 0 = No stuffing error occurred during a previous transfer. 1 = A stuffing error occurred during a previous transfer. A form error results from the detection of more than five consecutive bit with the same polarity. This flag is automatically cleared by reading CAN_SR register. * AERR: Acknowledgment Error 0 = No acknowledgment error occurred during a previous transfer. 1 = An acknowledgment error occurred during a previous transfer. An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. This flag is automatically cleared reading CAN_SR register. * FERR: Form Error 0 = No form error occurred during a previous transfer 1 = A form error occurred during a previous transfer A form error results from violations on one or more of the fixed form of the following bit fields: - CRC delimiter - ACK delimiter - End of frame - Error delimiter - Overload delimiter This flag is automatically cleared by reading CAN_SR register. * BERR: Bit Error 0 = No bit error occurred during a previous transfer. 1 = A bit error occurred during a previous transfer.
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A bit error is set when the bit value monitored on the line is different from the bit value sent. This flag is automatically cleared by reading CAN_SR register. * RBSY: Receiver busy 0 = CAN receiver is not receiving a frame. 1 = CAN receiver is receiving a frame. Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving. * TBSY: Transmitter busy 0 = CAN transmitter is not transmitting a frame. 1 = CAN transmitter is transmitting a frame. Transmitter busy. This status bit is set by hardware while CAN transmitter is generating a frame (remote, data, overload or error frame). It is automatically reset when CAN is not transmitting. * OVLSY: Overload busy 0 = CAN transmitter is not transmitting an overload frame. 1 = CAN transmitter is transmitting a overload frame. It is automatically reset when the bus is not transmitting an overload frame.
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39.8.6 Name: Access Type:
31 - 23 - 15 - 7 -
CAN Baudrate Register CAN_BR Read/Write
30 - 22 29 - 21 28 - 20 27 - 19 BRP 11 - 3 - 26 - 18 25 - 17 24 SMP 16
14 - 6
13 SJW 5 PHASE1
12
10
9 PROPAG 1 PHASE2
8
4
2
0
Any modification on one of the fields of the CANBR register must be done while CAN module is disabled. * PHASE2: Phase 2 segment This phase is used to compensate the edge phase error. t PHS2 = t CSC x ( PHASE2 + 1 ) * PHASE1: Phase 1 segment This phase is used to compensate for edge phase error. t PHS1 = t CSC x ( PHASE1 + 1 ) * PROPAG: Programming time segment This part of the bit time is used to compensate for the physical delay times within the network. t PRS = t CSC x ( PROPAG + 1 ) * SJW: Re-synchronization jump width To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization. t SJW = t CSC x ( SJW + 1 ) * BRP: Baudrate Prescaler. This field allows user to program the period of the CAN system clock to determine the individual bit timing. Tcsc = (BRP + 1) / MCK * SMP: Sampling Mode 0 = The incoming bit stream is sampled once at sample point. 1 = The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. SMP Sampling Mode is automatically disabled if BRP = 0.
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39.8.7 Name: Access Type:
31 - 23 - 15 TIMER15 7 TIMER7
CAN Timer Register CAN_TIM Read-only
30 - 22 - 14 TIMER14 6 TIMER6 29 - 21 - 13 TIMER13 5 TIMER5 28 - 20 - 12 TIMER12 4 TIMER4 27 - 19 - 11 TIMER11 3 TIMER3 26 - 18 - 10 TIMER10 2 TIMER2 25 - 17 - 9 TIMER9 1 TIMER1 24 - 16 - 8 TIMER8 0 TIMER0
* TIMERx: Timer This field represents the internal CAN controller 16-bit timer value.
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39.8.8 Name: Access Type:
31 - 23 - 15
MTIMESTAMP 15
CAN Timestamp Register CAN_TIMESTP Read-only
30 - 22 - 14
MTIMESTAMP 14
29 - 21 - 13
MTIMESTAMP 13
28 - 20 - 12
MTIMESTAMP 12
27 - 19 - 11
MTIMESTAMP 11
26 - 18 - 10
MTIMESTAMP 10
25 - 17 - 9
MTIMESTAMP 9
24 - 16 - 8
MTIMESTAMP 8
7
MTIMESTAMP 7
6
MTIMESTAMP 6
5
MTIMESTAMP 5
4
MTIMESTAMP 4
3
MTIMESTAMP 3
2
MTIMESTAMP 2
1
MTIMESTAMP 1
0
MTIMESTAMP 0
* MTIMESTAMPx: Timestamp This field represents the internal CAN controller 16-bit timer value. If the TEOF bit is cleared in the CAN_MR register, the internal Timer Counter value is captured in the MTIMESTAMP field at each start of frame. Else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in the CAN_SR register. If the TSTP mask in the CAN_IMR register is set, an interrupt is generated while TSTP flag is set in the CAN_SR register. This flag is cleared by reading the CAN_SR register.
Note: The CAN_TIMESTP register is reset when the CAN is disabled then enabled thanks to the CANEN bit in the CAN_MR.
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39.8.9 Name: Access Type:
31 - 23
CAN Error Counter Register CAN_ECR Read-only
30 - 22 29 - 21 28 - 20 TEC 15 - 7 14 - 6 13 - 5 12 - 4 REC 11 - 3 10 - 2 9 - 1 8 - 0 27 - 19 26 - 18 25 - 17 24 - 16
* REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG. When a receiver detects a dominant bit as the first bit after sending an ERROR FLAG, REC is increased by 8. When a receiver detects a BIT ERROR while sending an ACTIVE ERROR FLAG, REC is increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits, each receiver increases its REC by 8. After successful reception of a message, REC is decreased by 1 if it was between 1 and 127. If REC was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127. * TEC: Transmit Error Counter When a transmitter sends an ERROR FLAG, TEC is increased by 8 except when - the transmitter is error passive and detects an ACKNOWLEDGMENT ERROR because of not detecting a dominant ACK and does not detect a dominant bit while sending its PASSIVE ERROR FLAG. - the transmitter sends an ERROR FLAG because a STUFF ERROR occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant. When a transmitter detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG, the TEC will be increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits every transmitter increases its TEC by 8. After a successful transmission the TEC is decreased by 1 unless it was already 0.
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39.8.10 Name: Access Type:
31 TIMRST 23 - 15 - 7 MB7
CAN Transfer Command Register CAN_TCR Write-only
30 - 22 - 14 - 6 MB6 29 - 21 - 13 - 5 MB5 28 - 20 - 12 - 4 MB4 27 - 19 - 11 - 3 MB3 26 - 18 - 10 - 2 MB2 25 - 17 - 9 - 1 MB1 24 - 16 - 8 - 0 MB0
This register initializes several transfer requests at the same time. * MBx: Transfer Request for Mailbox x Table 39-3.
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description It receives the next message. This triggers a new reception. Sends data prepared in the mailbox as soon as possible. Sends a remote frame. Sends data prepared in the mailbox after receiving a remote frame from a consumer.
This flag clears the MRDY and MABT flags in the corresponding CAN_MSRx register. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mailbox with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., MB0 will be transferred before MB1). * TIMRST: Timer Reset Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This command is useful in Time Triggered mode.
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39.8.11 Name: Access Type:
31 - 23 - 15 - 7 MB7
CAN Abort Command Register CAN_ACR Write-only
30 - 22 - 14 - 6 MB6 29 - 21 - 13 - 5 MB5 28 - 20 - 12 - 4 MB4 27 - 19 - 11 - 3 MB3 26 - 18 - 10 - 2 MB2 25 - 17 - 9 - 1 MB1 24 - 16 - 8 - 0 MB0
This register initializes several abort requests at the same time. * MBx: Abort Request for Mailbox x Table 39-4.
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Cancels transfer request if the message has not been transmitted to the CAN transceiver. Cancels the current transfer before the remote frame has been sent. Cancels the current transfer. The next remote frame is not serviced.
It is possible to set MACR field (in the CAN_MCRx register) for each mailbox
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39.8.12 Name: Access Type:
31 - 23 - 15 MTIMEMARK 15 7
MTIMEMARK7
CAN Message Mode Register CAN_MMRx Read/Write
30 - 22 - 14 MTIMEMARK 14 6
MTIMEMARK6
29 - 21 - 13 MTIMEMARK 13 5
MTIMEMARK5
28 - 20 - 12 MTIMEMARK 12 4
MTIMEMARK4
27 - 19
26
25 MOT
24
18 PRIOR
17
16
11 MTIMEMARK 11 3
MTIMEMARK3
10 MTIMEMARK 10 2
MTIMEMARK2
9
MTIMEMARK9
8
MTIMEMARK8
1
MTIMEMARK1
0
MTIMEMARK0
* MTIMEMARK: Mailbox Timemark This field is active in Time Triggered Mode. Transmit operations are allowed when the internal timer counter reaches the Mailbox Timemark. See "Transmitting within a Time Window" on page 555. In Timestamp Mode, MTIMEMARK is set to 0. * PRIOR: Mailbox Priority This field has no effect in receive and receive with overwrite modes. In these modes, the mailbox with the lowest number is serviced first. When several mailboxes try to transmit a message at the same time, the mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 is serviced before MBx 15 if they have the same priority). * MOT: Mailbox Object Type This field allows the user to define the type of the mailbox. All mailboxes are independently configurable. Five different types are possible for each mailbox:
MOT 0 0 0 0 0 1 Mailbox Object Type Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. Transmit mailbox. Mailbox is configured for transmission. Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. Reserved
0 0 1
1 1 0
0 1 0
1 1
0 1
1 X
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39.8.13 Name: Access Type:
31 - 23
CAN Message Acceptance Mask Register CAN_MAMx Read/Write
30 - 22 29 MIDE 21 MIDvA 28 27 26 MIDvA 18 25 24
20
19
17 MIDvB
16
15
14
13
12 MIDvB
11
10
9
8
7
6
5
4 MIDvB
3
2
1
0
To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MAMx registers. * MIDvB: Complementary bits for identifier in extended frame mode Acceptance mask for corresponding field of the message IDvB register of the mailbox. * MIDvA: Identifier for standard frame mode Acceptance mask for corresponding field of the message IDvA register of the mailbox. * MIDE: Identifier Version 0= Compares IDvA from the received frame with the CAN_MIDx register masked with CAN_MAMx register. 1= Compares IDvA and IDvB from the received frame with the CAN_MIDx register masked with CAN_MAMx register.
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39.8.14 Name: Access Type:
31 - 23
CAN Message ID Register CAN_MIDx Read/Write
30 - 22 29 MIDE 21 MIDvA 28 27 26 MIDvA 18 25 24
20
19
17 MIDvB
16
15
14
13
12 MIDvB
11
10
9
8
7
6
5
4 MIDvB
3
2
1
0
To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers. * MIDvB: Complementary bits for identifier in extended frame mode If MIDE is cleared, MIDvB value is 0. * MIDE: Identifier Version This bit allows the user to define the version of messages processed by the mailbox. If set, mailbox is dealing with version 2.0 Part B messages; otherwise, mailbox is dealing with version 2.0 Part A messages. * MIDvA: Identifier for standard frame mode
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39.8.15 Name: Access Type:
31 - 23
CAN Message Family ID Register CAN_MFIDx Read-only
30 - 22 29 - 21 28 27 26 MFID 18 25 24
20 MFID
19
17
16
15
14
13
12 MFID
11
10
9
8
7
6
5
4 MFID
3
2
1
0
* MFID: Family ID This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below. As an example:
CAN_MIDx = 0x305A4321 CAN_MAMx = 0x3FF0F0FF CAN_MFIDx = 0x000000A3
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39.8.16 Name: Access Type:
31 - 23 MRDY 15
MTIMESTAMP 15
CAN Message Status Register CAN_MSRx Read only
30 - 22 MABT 14
MTIMESTAMP 14
29 - 21 - 13
MTIMESTAMP 13
28 - 20 MRTR 12
MTIMESTAMP 12
27 - 19
26 - 18 MDLC
25 - 17
24 MMI 16
11
MTIMESTAMP 11
10
MTIMESTAMP 10
9
MTIMESTAMP 9
8
MTIMESTAMP 8
7
MTIMESTAMP 7
6
MTIMESTAMP 6
5
MTIMESTAMP 5
4
MTIMESTAMP 4
3
MTIMESTAMP 3
2
MTIMESTAMP 2
1
MTIMESTAMP 1
0
MTIMESTAMP 0
These register fields are updated each time a message transfer is received or aborted. MMI is cleared by reading the CAN_MSRx register. MRDY, MABT are cleared by writing MTCR or MACR in the CAN_MCRx register. Warning: MRTR and MDLC state depends partly on the mailbox object type. * MTIMESTAMP: Timer value This field is updated only when time-triggered operations are disabled (TTM cleared in CAN_MR register). If the TEOF field in the CAN_MR register is cleared, TIMESTAMP is the internal timer value at the start of frame of the last message received or sent by the mailbox. If the TEOF field in the CAN_MR register is set, TIMESTAMP is the internal timer value at the end of frame of the last message received or sent by the mailbox. In Time Triggered Mode, MTIMESTAMP is set to 0. * MDLC: Mailbox Data Length Code
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Length of the first mailbox message received Length of the last mailbox message received No action Length of the mailbox message received Length of the mailbox message to be sent after the remote frame reception
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* MRTR: Mailbox Remote Transmission Request
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description The first frame received has the RTR bit set. The last frame received has the RTR bit set. Reserved Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 1. Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 0.
* MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0 = Previous transfer is not aborted. 1 = Previous transfer has been aborted. This flag is cleared by writing to CAN_MCRx register
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Reserved Reserved Previous transfer has been aborted The remote frame transfer request has been aborted. The response to the remote frame transfer has been aborted.
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* MRDY: Mailbox Ready An interrupt is triggered when MRDY is set. 0 = Mailbox data registers can not be read/written by the software application. CAN_MDx are locked by the CAN_MDx. 1 = Mailbox data registers can be read/written by the software application. This flag is cleared by writing to CAN_MCRx register.
Mailbox Object Type Receive Description At least one message has been received since the last mailbox transfer order. Data from the first frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. At least one frame has been received since the last mailbox transfer order. Data from the last frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. Mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1. At least one message has been received since the last mailbox transfer order. Data from the first message received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. A remote frame has been received, mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1.
Receive with overwrite
Transmit
Consumer
Producer
* MMI: Mailbox Message Ignored 0 = No message has been ignored during the previous transfer 1 = At least one message has been ignored during the previous transfer Cleared by reading the CAN_MSRx register.
Mailbox Object Type Receive Description Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message. Set when at least two messages intended for the mailbox have been sent. The last one is available in the mailbox data register. Previous ones have been lost. Reserved A remote frame has been sent by the mailbox but several messages have been received. The first one is available in the mailbox data register. Others have been ignored. Another mailbox with a lower priority may have accepted the message. A remote frame has been received, but no data are available to be sent.
Receive with overwrite Transmit Consumer Producer
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39.8.17 Name: Access Type:
31
CAN Message Data Low Register CAN_MDLx Read/Write
30 29 28 MDL 27 26 25 24
23
22
21
20 MDL
19
18
17
16
15
14
13
12 MDL
11
10
9
8
7
6
5
4 MDL
3
2
1
0
* MDL: Message Data Low Value When MRDY field is set in the CAN_MSRx register, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDL value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set.
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39.8.18 Name: Access Type:
31
CAN Message Data High Register CAN_MDHx Read/Write
30 29 28 MDH 27 26 25 24
23
22
21
20 MDH
19
18
17
16
15
14
13
12 MDH
11
10
9
8
7
6
5
4 MDH
3
2
1
0
* MDH: Message Data High Value When MRDY field is set in the CAN_MSRx register, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDH value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set.
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39.8.19 Name: Access Type:
31 - 23 MTCR 15 - 7 -
CAN Message Control Register CAN_MCRx Write-only
30 - 22 MACR 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 MRTR 12 - 4 - 27 - 19 26 - 18 MDLC 11 - 3 - 10 - 2 - 9 - 1 - 8 - 0 - 25 - 17 24 - 16
* MDLC: Mailbox Data Length Code
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action. No action. Length of the mailbox message. No action. Length of the mailbox message to be sent after the remote frame reception.
* MRTR: Mailbox Remote Transmission Request
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Set the RTR bit in the sent frame No action, the RTR bit in the sent frame is set automatically No action
Consumer situations can be handled automatically by setting the mailbox object type in Consumer. This requires only one mailbox. It can also be handled using two mailboxes, one in reception, the other in transmission. The MRTR and the MTCR bits must be set in the same time.
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* MACR: Abort Request for Mailbox x
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Cancels transfer request if the message has not been transmitted to the CAN transceiver. Cancels the current transfer before the remote frame has been sent. Cancels the current transfer. The next remote frame will not be serviced.
It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR register. * MTCR: Mailbox Transfer Command
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Allows the reception of the next message. Triggers a new reception. Sends data prepared in the mailbox as soon as possible. Sends a remote transmission frame. Sends data prepared in the mailbox after receiving a remote frame from a Consumer.
This flag clears the MRDY and MABT flags in the CAN_MSRx register. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn. The mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 will be serviced before MBx 15 if they have the same priority). It is possible to set MTCR for several mailboxes at the same time by writing to the CAN_TCR register.
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40. Ethernet MAC 10/100 (EMAC)
40.1 Overview
The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. The statistics register block contains registers for counting various types of event associated with transmit and receive operations. These registers, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with IEEE 802.3.
40.2
Block Diagram
Figure 40-1. EMAC Block Diagram
Address Checker
APB Slave
Register Interface
Statistics Registers
MDIO
Control Registers
DMA Interface
RX FIFO TX FIFO
Ethernet Receive
ASB Master MII/RMII
Ethernet Transmit
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40.3
Functional Description
Figure 40-1 illustrates the different blocks of the EMAC module. The control registers drive the MDIO interface, setup up DMA activity, start frame transmission and select modes of operation such as full- or half-duplex. The receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the address checking block and DMA interface. The transmit block takes data from the DMA interface, adds preamble and, if necessary, pad and FCS, and transmits data according to the CSMA/CD (carrier sense multiple access with collision detect) protocol. The start of transmission is deferred if CRS (carrier sense) is active. If COL (collision) becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random back off. CRS and COL have no effect in full duplex mode. The DMA block connects to external memory through its ASB bus interface. It contains receive and transmit FIFOs for buffering frame data. It loads the transmit FIFO and empties the receive FIFO using ASB bus master operations. Receive data is not sent to memory until the address checking logic has determined that the frame should be copied. Receive or transmit frames are stored in one or more buffers. Receive buffers have a fixed length of 128 bytes. Transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. The DMA block manages the transmit and receive framebuffer queues. These queues can hold multiple frames.
40.3.1
Memory Interface Frame data is transferred to and from the EMAC through the DMA interface. All transfers are 32bit words and may be single accesses or bursts of 2, 3 or 4 words. Burst accesses do not cross sixteen-byte boundaries. Bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer. The DMA controller performs six types of operation on the bus. In order of priority, these are: 1. Receive buffer manager write 2. Receive buffer manager read 3. Transmit data DMA read 4. Receive data DMA write 5. Transmit buffer manager read 6. Transmit buffer manager write
40.3.1.1
FIFO The FIFO depths are 28 bytes and 28 bytes and area function of the system clock speed, memory latency and network speed. Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when the FIFO contains four words and has space for three more. For transmit, a bus request is generated when there is space for four words, or when there is space for two words if the next transfer is to be only one or two words. Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (12 bytes) of data.
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At 100 Mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. In addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 60 MHz master clock this takes 100 ns, making the bus latency requirement 860 ns. 40.3.1.2 Receive Buffers Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is 128 bytes long. The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. The receive buffer start location is a word address. For the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. If the start location of the buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes. Each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. If the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes except for the "start of frame" bit and the offset bits, if appropriate. Bit zero of the address field is written to one to show the buffer has been used. The receive buffer manager then reads the location of the next receive buffer and fills that with receive frame data. The final buffer descriptor status word contains the complete frame status. Refer to Table 40-1 for details of the receive buffer descriptor list. Table 40-1.
Bit
Receive Buffer Descriptor Entry
Function Word 0
31:2 1 0
Address of beginning of buffer Wrap - marks last descriptor in receive buffer descriptor list. Ownership - needs to be zero for the EMAC to write data to the receive buffer. The EMAC sets this to one once it has successfully written a frame to memory. Software has to clear this bit before the buffer can be used again. Word 1
31 30 29 28 27 26 25 24 23 22 21 20 19:17
Global all ones broadcast address detected Multicast hash match Unicast hash match External address match Reserved for future use Specific address register 1 match Specific address register 2 match Specific address register 3 match Specific address register 4 match Type ID match VLAN tag detected (i.e., type id of 0x8100) Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier) VLAN priority (only valid if bit 21 is set)
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Table 40-1.
Bit 16 15 14
Receive Buffer Descriptor Entry (Continued)
Function Concatenation format indicator (CFI) bit (only valid if bit 21 is set) End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14. Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame. Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. Updated with the current values of the network configuration register. If jumbo frame mode is enabled through bit 3 of the network configuration register, then bits 13:12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length. Length of frame including FCS (if selected). Bits 13:12 are also used if jumbo frame mode is selected.
13:12
11:0
To receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. Bit zero must be written with zero. Bit one is the wrap bit and indicates the last entry in the list. The start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. As soon as the receive block starts writing received frame data to the receive FIFO, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register. If the filter block then indicates that the frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. If the current buffer pointer has its wrap bit set or is the 1024th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. Otherwise, the next receive buffer location is read from the next word in memory. There is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. This is added with the value originally written to the receive buffer queue pointer register to produce a pointer into the list. A read of the receive buffer queue pointer register returns the pointer value, which is the queue entry currently being accessed. The counter is reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. The value written to the receive buffer pointer register may be any word-aligned address, provided that there are at least 2048 word locations available between the pointer and the top of the memory. Section 3.6 of the AMBA 2.0 specification states that bursts should not cross 1K boundaries. As receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. As receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used. If a receive error is detected the receive buffer currently being written is recovered. Previous buffers are not recovered. Software should search through the used bits in the buffer descriptors to find out how many frames have been received. It should be checking the start-offrame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes continuously as more buffers are used. For CRC errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored
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in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. For a properly working Ethernet system, there should be no excessively long frames or frames greater than 128 bytes with CRC/FCS errors. Collision fragments are less than 128 bytes long. Therefore, it is a rare occurrence to find a frame fragment in a receive buffer. If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in the receive status register and triggers an interrupt. If bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented. A receive overrun condition occurs when bus was not granted in time or because HRESP was not OK (bus error). In a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame received with an address that is recognized reuses the buffer. If bit 17 of the network configuration register is set, the FCS of received frames shall not be copied to memory. The frame length indicated in the receive status field shall be reduced by four bytes in this case. 40.3.1.3 Transmit Buffer Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum number of buffers permitted for each transmit frame is 128. The start location for each transmit buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer register. Each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. Frames can be transmitted with or without automatic CRC generation. If CRC is automatically generated, pad is also automatically generated to take frames to a minimum length of 64 bytes. Table 40-2 on page 590 defines an entry in the transmit buffer descriptor list. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits 31 to 0 in the first word of each list entry. The second transmit buffer descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted with CRC and whether the buffer is the last buffer in the frame. After transmission, the control bits are written back to the second word of the first buffer along with the "used" bit and other status information. Bit 31 is the "used" bit which must be zero when the control word is read if transmission is to happen. It is written to one when a frame has been transmitted. Bits 27, 28 and 29 indicate various transmit error conditions. Bit 30 is the "wrap" bit which can be set for any buffer within a frame. If no wrap bit is encountered after 1024 descriptors, the queue pointer rolls over to the start in a similar fashion to the receive queue. The transmit buffer queue pointer register must not be written while transmit is active. If a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. Note that disabling receive does not have the same effect on the receive queue pointer. 589
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Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start bit of the network control register. Transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control register. (Transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) Rewriting the start bit while transmission is active is allowed. Transmission control is implemented with a Tx_go variable which is readable in the transmit status register at bit location 3. The Tx_go variable is reset when: - transmit is disabled - a buffer descriptor with its ownership bit set is read - a new value is written to the transmit buffer queue pointer register - bit 10, tx_halt, of the network control register is written - there is a transmit error such as too many retries or a transmit underrun. To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take effect until any ongoing transmit finishes. If a collision occurs during transmission of a multibuffer frame, transmission automatically restarts from the first buffer of the frame. If a "used" bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, tx_er is asserted and the FCS is bad. If transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. Software needs to re-initialize the transmit queue after a transmit error. If transmission stops due to a "used" bit being read at the start of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written Table 40-2.
Bit
Transmit Buffer Descriptor Entry
Function Word 0
31:0
Byte Address of buffer Word 1 Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer of a frame once it has been successfully transmitted. Software has to clear this bit before the buffer can be used again. Note: This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used. Wrap. Marks last descriptor in transmit buffer descriptor list. Retry limit exceeded, transmit error detected Transmit underrun, occurs either when hresp is not OK (bus error) or the transmit data could not be fetched in time or when buffers are exhausted in mid frame. Buffers exhausted in mid frame Reserved No CRC. When set, no CRC is appended to the current frame. This bit only needs to be set for the last buffer of a frame. Last buffer. When set, this bit indicates the last buffer in the current frame has been reached. Reserved Length of buffer
31
30 29 28 27 26:17 16 15 14:11 10:0
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40.3.2 Transmit Block This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. Data is transmitted least significant nibble first. If necessary, padding is added to increase the frame length to 60 bytes. CRC is calculated as a 32-bit polynomial. This is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. If the No CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended. In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed. The back-off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are made if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the tx_er signal is asserted. For a properly configured system, this should never happen. If the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half-duplex mode. 40.3.3 Pause Frame Support The start of an 802.3 pause frame is as follows: Table 40-3. Start of an 802.3 Pause Frame
Source Address 6 bytes Type (Mac Control Frame) 0x8808 Pause Opcode 0x0001 Pause Time 2 bytes
Destination Address 0x0180C2000001
The network configuration register contains a receive pause enable bit (13). If a valid pause frame is received, the pause time register is updated with the frame's pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. An interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. If bit 13 is set in the network configuration register and the value of the pause time register is non-zero, no new frame is transmitted until the pause time register has decremented to zero. The loading of a new pause time, and hence the pausing of transmission, only occurs when the EMAC is configured for full-duplex operation. If the EMAC is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is still triggered.
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A valid pause frame is defined as having a destination address that matches either the address stored in specific address register 1 or matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause opcode of 0x0001. Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause frames received increment the Pause Frame Received statistic register. The pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. For test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. If the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of whether transmission has stopped or not. An interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the interrupt mask register). 40.3.4 Receive Block The receive block checks for valid preamble, FCS, alignment and length, presents received frames to the DMA block and stores the frames destination address for use by the address checking block. If, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the DMA block. The DMA block then ceases sending data to memory. At the end of frame reception, the receive block indicates to the DMA block whether the frame is good or bad. The DMA block recovers the current receive buffer if the frame was bad. The receive block signals the register block to increment the alignment error, the CRC (FCS) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of up to 10240 bytes in size. This operation does not form part of the IEEE802.3 specification and is disabled by default. When jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 40.3.5 Address Checking Block The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory. Whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame's destination address. In this implementation of the EMAC, the frame's source address is not checked. Provided that bit 18 of the Network Configuration register is not set, a frame is not copied to memory if the EMAC is transmitting in half duplex mode at the time a destination address is received. If bit 18 of the Network Configuration register is set, frames can be received while transmitting in half-duplex mode. Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, the LSB of the first byte of the frame, is the group/individual bit: this is One for multicast addresses and Zero for unicast. The All Ones address is the broadcast address, and a special case of multicast. The EMAC supports recognition of four specific addresses. Each specific address requires two registers, specific address register bottom and specific address register top. Specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. The addresses stored can be specific, group, local or universal.
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The destination address of received frames is compared against the data stored in the specific address registers once they have been activated. The addresses are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. If a receive frame address matches an active address, the frame is copied to memory. The following example illustrates the use of the address match registers for a MAC address of 21:43:65:87:A9:CB. Preamble 55 SFD D5 DA (Octet0 - LSB) 21 DA(Octet 1) 43 DA(Octet 2) 65 DA(Octet 3) 87 DA(Octet 4) A9 DA (Octet5 - MSB) CB SA (LSB) 00 SA 00 SA 00 SA 00 SA 00 SA (MSB) 43 SA (LSB) 21 The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown. For a successful match to specific address 1, the following address matching registers must be set up: * Base address + 0x98 0x87654321 (Bottom) * Base address + 0x9C 0x0000CBA9 (Top) And for a successful match to the Type ID register, the following should be set up: * Base address + 0xB8 0x00004321 40.3.6 Broadcast Address The broadcast address of 0xFFFFFFFFFFFF is recognized if the `no broadcast' bit in the network configuration register is zero. 40.3.7 Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit 593
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index into the 64-bit hash register using the following hash function. The hash function is an exclusive or of every sixth bit of the destination address.
hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. If the hash index points to a bit that is set in the hash register, then the frame is matched according to whether the frame is multicast or unicast. A multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in the hash register. A unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register. To receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register. 40.3.8 Copy All Frames (or Promiscuous Mode) If the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory. For example, frames that are too long, too short, or have FCS errors or rx_er asserted during reception are discarded and all others are received. Frames with FCS errors are copied to memory if bit 19 in the network configuration register is set. 40.3.9 Type ID Checking The contents of the type_id register are compared against the length/type ID of received frames (i.e., bytes 13 and 14). Bit 22 in the receive buffer descriptor status is set if there is a match. The reset state of this register is zero which is unlikely to match the length/type ID of any valid Ethernet frame.
Note: A type ID match does not affect whether a frame is copied to memory.
40.3.10
VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 40-4. 802.1Q VLAN Tag
TCI (Tag Control Information) 16 bits First 3 bits priority, then CFI bit, last 12 bits VID
TPID (Tag Protocol Identifier) 16 bits 0x8100
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The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame. The MAC can support frame lengths up to 1536 bytes, 18 bytes more than the original Ethernet maximum frame length of 1518 bytes. This is achieved by setting bit 8 in the network configuration register. The following bits in the receive buffer descriptor status word give information about VLAN tagged frames: * Bit 21 set if receive frame is VLAN tagged (i.e. type id of 0x8100) * Bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit 20 is set bit 21 is set also.) * Bit 19, 18 and 17 set to priority if bit 21 is set * Bit 16 set to CFI if bit 21 is set 40.3.11 PHY Maintenance The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration. The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 MCK cycles later when bit ten is set to zero, and bit eleven is set to one in the network configuration register). An interrupt is generated as this bit is set. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bits[31:28] should be written as 0x0011. For a description of MDC generation, see the network configuration register in the "Network Control Register" on page 602. 40.3.12 Media Independent Interface The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the EMAC_USRIO register controls the interface that is selected. When this bit is set, the RMII interface is selected, else the MII interface is selected. The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in Table 40-5. Table 40-5.
Pin Name ETXCK_EREFCK ECRS ECOL ERXDV
Pin Configuration
MII ETXCK: Transmit Clock ECRS: Carrier Sense ECOL: Collision Detect ERXDV: Data Valid ECRSDV: Carrier Sense/Data Valid RMII EREFCK: Reference Clock
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Table 40-5.
ERX0 - ERX3 ERXER ERXCK ETXEN ETX0-ETX3 ETXER
Pin Configuration (Continued)
ERX0 - ERX3: 4-bit Receive Data ERXER: Receive Error ERXCK: Receive Clock ETXEN: Transmit Enable ETX0 - ETX3: 4-bit Transmit Data ETXER: Transmit Error ETXEN: Transmit Enable ETX0 - ETX1: 2-bit Transmit Data ERX0 - ERX1: 2-bit Receive Data ERXER: Receive Error
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It uses 2 bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV), and a 50 MHz Reference Clock (ETXCK_EREFCK) for 100Mb/s data rate. 40.3.12.1 RMII Transmit and Receive Operation The same signals are used internally for both the RMII and the MII operations. The RMII maps these signals in a more pin-efficient manner. The transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense and data valid signals are combined into the ECRSDV signal. This signal contains information on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and collision detect (ECOL) are not used in RMII mode.
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40.4
40.4.1 40.4.1.1
Programming Interface
Initialization Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1. Write to network control register to disable transmit and receive circuits. 2. Write to network control register to change loop-back mode. 3. Write to network control register to re-enable transmit or receive circuits.
Note: These writes to network control register cannot be combined in any way.
40.4.1.2
Receive Buffer List Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor entries as defined in "Receive Buffer Descriptor Entry" on page 587. It points to this data structure.
Figure 40-2. Receive Buffer List
Receive Buffer 0 Receive Buffer Queue Pointer (MAC Register) Receive Buffer 1
Receive Buffer N Receive Buffer Descriptor List (In memory) (In memory)
To create the list of buffers: 1. Allocate a number (n) of buffers of 128 bytes in system memory. 2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and create n entries in this list. Mark all entries in this list as owned by EMAC, i.e., bit 0 of word 0 set to 0. 3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1). 4. Write address of receive buffer descriptor entry to EMAC register receive_buffer queue pointer.
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5. The receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. 40.4.1.3 Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries (as defined in Table 40-2 on page 590) that points to this data structure. To create this list of buffers: 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. 2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory and create N entries in this list. Mark all entries in this list as owned by EMAC, i.e. bit 31 of word 1 set to 0. 3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit -- bit 30 in word 1 set to 1. 4. Write address of transmit buffer descriptor entry to EMAC register transmit_buffer queue pointer. 5. The transmit circuits can then be enabled by writing to the network control register. 40.4.1.4 Address Matching The EMAC register-pair hash address and the four specific address register-pairs must be written with the required values. Each register-pair comprises a bottom register and top register, with the bottom register being written first. The address matching is disabled for a particular register-pair after the bottom-register has been written and re-enabled when the top register is written. See "Address Checking Block" on page 592. for details of address matching. Each register-pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. 40.4.1.5 Interrupts There are 14 interrupt conditions that are detected within the EMAC. These are ORed to make a single interrupt. Depending on the overall system design, this may be passed through a further level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt handler (Refer to the AIC programmer datasheet). To ascertain which interrupt has been generated, read the interrupt status register. Note that this register clears itself when read. At reset, all interrupts are disabled. To enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. To disable an interrupt, write to interrupt disable register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled. 40.4.1.6 Transmitting Frames To set up a frame for transmission: 1. Enable transmit in the network control register. 2. Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte lengths can be used as long as they conclude on byte borders. 3. Set-up the transmit buffer list. 4. Set the network control register to enable transmission and enable interrupts.
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5. Write data for transmission into these buffers. 6. Write the address to transmit buffer descriptor queue pointer. 7. Write control and length to word one of the transmit buffer descriptor entry. 8. Write to the transmit start bit in the network control register. 40.4.1.7 Receiving Frames When a frame is received and the receive circuits are enabled, the EMAC checks the address and, in the following cases, the frame is written to system memory: * if it matches one of the four specific address registers. * if it matches the hash address function. * if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed. * if the EMAC is configured to copy all frames. The register receive buffer queue pointer points to the next entry (see Table 40-1 on page 587) and the EMAC uses this as the address in system memory to write the frame to. Once the frame has been completely and successfully received and written to system memory, the EMAC then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. Once this is complete an interrupt receive complete is set. Software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not available is set. If the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.
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40.5
Ethernet MAC 10/100 (EMAC) User Interface
Ethernet MAC 10/100 (EMAC) Register Mapping
Register Network Control Register Network Configuration Register Network Status Register Reserved Reserved Transmit Status Register Receive Buffer Queue Pointer Register Transmit Buffer Queue Pointer Register Receive Status Register Interrupt Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Phy Maintenance Register Pause Time Register Pause Frames Received Register Frames Transmitted Ok Register Single Collision Frames Register Multiple Collision Frames Register Frames Received Ok Register Frame Check Sequence Errors Register Alignment Errors Register Deferred Transmission Frames Register Late Collisions Register Excessive Collisions Register Transmit Underrun Errors Register Carrier Sense Errors Register Receive Resource Errors Register Receive Overrun Errors Register Receive Symbol Errors Register Excessive Length Errors Register Receive Jabbers Register Undersize Frames Register SQE Test Errors Register Received Length Field Mismatch Register EMAC_TSR EMAC_RBQP EMAC_TBQP EMAC_RSR EMAC_ISR EMAC_IER EMAC_IDR EMAC_IMR EMAC_MAN EMAC_PTR EMAC_PFR EMAC_FTO EMAC_SCF EMAC_MCF EMAC_FRO EMAC_FCSE EMAC_ALE EMAC_DTF EMAC_LCOL EMAC_ECOL EMAC_TUND EMAC_CSE EMAC_RRE EMAC_ROV EMAC_RSE EMAC_ELE EMAC_RJA EMAC_USF EMAC_STE EMAC_RLE Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_3FFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Name EMAC_NCR EMAC_NCFG EMAC_NSR Access Read/Write Read/Write Read-only Reset Value 0 0x800 -
Table 40-6.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 0x88
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Table 40-6.
Offset 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xC0 0xC8-0xF8 0xC8 - 0xFC
Ethernet MAC 10/100 (EMAC) Register Mapping (Continued)
Register Hash Register Bottom [31:0] Register Hash Register Top [63:32] Register Specific Address 1 Bottom Register Specific Address 1 Top Register Specific Address 2 Bottom Register Specific Address 2 Top Register Specific Address 3 Bottom Register Specific Address 3 Top Register Specific Address 4 Bottom Register Specific Address 4 Top Register Type ID Checking Register User Input/output Register Reserved Reserved Name EMAC_HRB EMAC_HRT EMAC_SA1B EMAC_SA1T EMAC_SA2B EMAC_SA2T EMAC_SA3B EMAC_SA3T EMAC_SA4B EMAC_SA4T EMAC_TID EMAC_USRIO - - Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write - - Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - -
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40.5.1
Network Control Register EMAC_NCR Read/Write
30 - 22 - 14 - 6 INCSTAT 29 - 21 - 13 - 5 CLRSTAT 28 - 20 - 12 - 4 MPE 27 - 19 - 11 - 3 TE 26 - 18 - 10 THALT 2 RE 25 - 17 - 9 TSTART 1 LLB 24 - 16 - 8 BP 0 LB
Register Name: Access Type:
31 - 23 - 15 - 7 WESTAT
* LB: LoopBack Asserts the loopback signal to the PHY. * LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4. rx_clk and tx_clk may glitch as the EMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. * RE: Receive enable When set, enables the EMAC to receive data. When reset, frame reception stops immediately and the receive FIFO is cleared. The receive queue pointer register is unaffected. * TE: Transmit enable When set, enables the Ethernet transmitter to send data. When reset transmission, stops immediately, the transmit FIFO and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descriptor list. * MPE: Management port enable Set to one to enable the management port. When zero, forces MDIO to high impedance state and MDC low. * CLRSTAT: Clear statistics registers This bit is write only. Writing a one clears the statistics registers. * INCSTAT: Increment statistics registers This bit is write only. Writing a one increments all the statistics registers by one for test purposes. * WESTAT: Write enable for statistics registers Setting this bit to one makes the statistics registers writable for functional test purposes. * BP: Back pressure If set in half duplex mode, forces collisions on all received frames. * TSTART: Start transmission Writing one to this bit starts transmission. * THALT: Transmit halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends. 602
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40.5.2 Network Configuration Register EMAC_NCFGR Read/Write
30 - 22 - 14 RBOF 7 UNI 6 MTI 29 - 21 - 13 PAE 5 NBC 28 - 20 - 12 RTY 4 CAF 27 - 19 IRXFCS 11 CLK 3 JFRAME 2 - 1 FD 26 - 18 EFRHD 10 25 - 17 DRFCS 9 24 - 16 RLCE 8 BIG 0 SPD
Register Name: Access Type:
31 - 23 - 15
* SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin. * FD: Full Duplex If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin. * CAF: Copy All Frames When set to 1, all valid frames are received. * JFRAME: Jumbo Frames Set to one to enable jumbo frames of up to 10240 bytes to be accepted. * NBC: No Broadcast When set to 1, frames addressed to the broadcast address of all ones are not received. * MTI: Multicast Hash Enable When set, multicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. * UNI: Unicast Hash Enable When set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. * BIG: Receive 1536 bytes frames Setting this bit means the EMAC receives frames up to 1536 bytes in length. Normally, the EMAC would reject any frame above 1518 bytes.
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* CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations).
CLK 00 01 10 11 MDC MCK divided by 8 (MCK up to 20 MHz) MCK divided by 16 (MCK up to 40 MHz) MCK divided by 32 (MCK up to 80 MHz) MCK divided by 64 (MCK up to 160 MHz)
* RTY: Retry test Must be set to zero for normal operation. If set to one, the back off between collisions is always one slot time. Setting this bit to one helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. * PAE: Pause Enable When set, transmission pauses when a valid pause frame is received. * RBOF: Receive Buffer Offset Indicates the number of bytes by which the received data is offset from the start of the first receive buffer.
RBOF 00 01 10 11 Offset No offset from start of receive buffer One-byte offset from start of receive buffer Two-byte offset from start of receive buffer Three-byte offset from start of receive buffer
* RLCE: Receive Length field Checking Enable When set, frames with measured lengths shorter than their length fields are discarded. Frames containing a type ID in bytes 13 and 14 -- length/type ID = 0600 -- are not be counted as length errors. * DRFCS: Discard Receive FCS When set, the FCS field of received frames are not be copied to memory. * EFRHD: Enable Frames to be received in half-duplex mode while transmitting. * IRXFCS: Ignore RX FCS When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0.
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40.5.3 Network Status Register EMAC_NSR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 IDLE 25 - 17 - 9 - 1 MDIO 24 - 16 - 8 - 0 -
Register Name: Access Type:
31 - 23 - 15 - 7 -
* MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. * IDLE 0 = The PHY management logic is idle (i.e., has completed). 1 = The PHY logic is running.
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40.5.4
Transmit Status Register EMAC_TSR Read/Write
30 - 22 - 14 - 6 UND 29 - 21 - 13 - 5 COMP 28 - 20 - 12 - 4 BEX 27 - 19 - 11 - 3 TGO 26 - 18 - 10 - 2 RLE 25 - 17 - 9 - 1 COL 24 - 16 - 8 - 0 UBR
Register Name: Access Type:
31 - 23 - 15 - 7 -
This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. * UBR: Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. * COL: Collision Occurred Set by the assertion of collision. Cleared by writing a one to this bit. * RLE: Retry Limit exceeded Cleared by writing a one to this bit. * TGO: Transmit Go If high transmit is active. * BEX: Buffers exhausted mid frame If the buffers run out during transmission of a frame, then transmission stops, FCS shall be bad and tx_er asserted. Cleared by writing a one to this bit. * COMP: Transmit Complete Set when a frame has been transmitted. Cleared by writing a one to this bit. * UND: Transmit Underrun Set when transmit DMA was not able to read data from memory, either because the bus was not granted in time, because a not OK hresp(bus error) was returned or because a used bit was read midway through frame transmission. If this occurs, the transmitter forces bad CRC. Cleared by writing a one to this bit.
606
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.5 Receive Buffer Queue Pointer Register EMAC_RBQP Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 ADDR 4 3 2 1 - 0 - 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. Receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification. * ADDR: Receive buffer queue pointer address Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used.
607
6120A-ATARM-01-Sep-05
40.5.6
Transmit Buffer Queue Pointer Register EMAC_TBQP Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 ADDR 4 3 2 1 - 0 - 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. This register can only be written when bit 3 in the transmit status register is low. As transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification. * ADDR: Transmit buffer queue pointer address Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted.
608
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.7 Receive Status Register EMAC_RSR Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 OVR 25 - 17 - 9 - 1 REC 24 - 16 - 8 - 0 BNA
Register Name: Access Type:
31 - 23 - 15 - 7 -
This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. * BNA: Buffer Not Available An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit. * REC: Frame Received One or more frames have been received and placed in memory. Cleared by writing a one to this bit. * OVR: Receive Overrun The DMA block was unable to store the receive frame to memory, either because the bus was not granted in time or because a not OK hresp(bus error) was returned. The buffer is recovered if this happens. Cleared by writing a one to this bit.
609
6120A-ATARM-01-Sep-05
40.5.8
Interrupt Status Register EMAC_ISR Read/Write
30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 24 - 16 - 8 - 0 MFD
Register Name: Access Type:
31 - 23 - 15 - 7 TCOMP
1 RCOMP
* MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. * RCOMP: Receive Complete A frame has been stored in memory. Cleared on read. * RXUBR: Receive Used Bit Read Set when a receive buffer descriptor is read with its used bit set. Cleared on read. * TXUBR: Transmit Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. * TUND: Ethernet Transmit Buffer Underrun The transmit DMA did not fetch frame data in time for it to be transmitted or hresp returned not OK. Also set if a used bit is read mid-frame or when a new transmit queue pointer is written. Cleared on read. * RLE: Retry Limit Exceeded Cleared on read. * TXERR: Transmit Error Transmit buffers exhausted in mid-frame - transmit error. Cleared on read. * TCOMP: Transmit Complete Set when a frame has been transmitted. Cleared on read. * ROVR: Receive Overrun Set when the receive overrun status bit gets set. Cleared on read. * HRESP: Hresp not OK Set when the DMA block sees a bus error. Cleared on read. * PFR: Pause Frame Received Indicates a valid pause has been received. Cleared on a read. * PTZ: Pause Time Zero Set when the pause time register, 0x38 decrements to zero. Cleared on a read. 610
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.9 Interrupt Enable Register EMAC_IER Read/Write
30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 24 - 16 - 8 - 0 MFD
Register Name: Access Type:
31 - 23 - 15 - 7 TCOMP
1 RCOMP
* MFD: Management Frame sent Enable management done interrupt. * RCOMP: Receive Complete Enable receive complete interrupt. * RXUBR: Receive Used Bit Read Enable receive used bit read interrupt. * TXUBR: Transmit Used Bit Read Enable transmit used bit read interrupt. * TUND: Ethernet Transmit Buffer Underrun Enable transmit underrun interrupt. * RLE: Retry Limit Exceeded Enable retry limit exceeded interrupt. * TXERR Enable transmit buffers exhausted in mid-frame interrupt. * TCOMP: Transmit Complete Enable transmit complete interrupt. * ROVR: Receive Overrun Enable receive overrun interrupt. * HRESP: Hresp not OK Enable Hresp not OK interrupt. * PFR: Pause Frame Received Enable pause frame received interrupt. * PTZ: Pause Time Zero Enable pause time zero interrupt.
611
6120A-ATARM-01-Sep-05
40.5.10
Interrupt Disable Register EMAC_IDR Read/Write
30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 24 - 16 - 8 - 0 MFD
Register Name: Access Type:
31 - 23 - 15 - 7 TCOMP
1 RCOMP
* MFD: Management Frame sent Disable management done interrupt. * RCOMP: Receive Complete Disable receive complete interrupt. * RXUBR: Receive Used Bit Read Disable receive used bit read interrupt. * TXUBR: Transmit Used Bit Read Disable transmit used bit read interrupt. * TUND: Ethernet Transmit Buffer Underrun Disable transmit underrun interrupt. * RLE: Retry Limit Exceeded Disable retry limit exceeded interrupt. * TXERR Disable transmit buffers exhausted in mid-frame interrupt. * TCOMP: Transmit Complete Disable transmit complete interrupt. * ROVR: Receive Overrun Disable receive overrun interrupt. * HRESP: Hresp not OK Disable Hresp not OK interrupt. * PFR: Pause Frame Received Disable pause frame received interrupt. * PTZ: Pause Time Zero Disable pause time zero interrupt.
612
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.11 Interrupt Mask Register EMAC_IMR Read/Write
30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 24 - 16 - 8 - 0 MFD
Register Name: Access Type:
31 - 23 - 15 - 7 TCOMP
1 RCOMP
* MFD: Management Frame sent Management done interrupt masked. * RCOMP: Receive Complete Receive complete interrupt masked. * RXUBR: Receive Used Bit Read Receive used bit read interrupt masked. * TXUBR: Transmit Used Bit Read Transmit used bit read interrupt masked. * TUND: Ethernet Transmit Buffer Underrun Transmit underrun interrupt masked. * RLE: Retry Limit Exceeded Retry limit exceeded interrupt masked. * TXERR Transmit buffers exhausted in mid-frame interrupt masked. * TCOMP: Transmit Complete Transmit complete interrupt masked. * ROVR: Receive Overrun Receive overrun interrupt masked. * HRESP: Hresp not OK Hresp not OK interrupt masked. * PFR: Pause Frame Received Pause frame received interrupt masked. * PTZ: Pause Time Zero Pause time zero interrupt masked.
613
6120A-ATARM-01-Sep-05
40.5.12
PHY Maintenance Register EMAC_MAN Read/Write
30 SOF 29 RW 22 21 20 REGA 12 DATA 19 18 28 27 26 PHYA 17 CODE 11 10 9 8 16 25 24
Register Name: Access Type:
31
23 PHYA 15
14
13
7
6
5
4 DATA
3
2
1
0
* DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. * CODE: Must be written to 10. Reads as written. * REGA: Register Address Specifies the register in the PHY to access. * PHYA: PHY Address * RW: Read/Write 10 is read; 01 is write. Any other value is an invalid PHY management frame * SOF: Start of frame Must be written 01 for a valid frame.
614
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.13 Pause Time Register EMAC_PTR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 PTIME 7 6 5 4 PTIME 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
615
6120A-ATARM-01-Sep-05
40.5.14
Hash Register Bottom EMAC_HRB Read/Write
30 29 28 ADDR 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 ADDR
19
18
17
16
15
14
13
12 ADDR
11
10
9
8
7
6
5
4 ADDR
3
2
1
0
* ADDR: Bits 31:0 of the hash address register. See "Hash Addressing" on page 593.
40.5.15
Hash Register Top EMAC_HRT Read/Write
30 29 28 ADDR 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 ADDR
19
18
17
16
15
14
13
12 ADDR
11
10
9
8
7
6
5
4 ADDR
3
2
1
0
* ADDR: Bits 63:32 of the hash address register. See "Hash Addressing" on page 593.
616
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.16 Specific Address 1 Bottom Register EMAC_SA1B Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
40.5.17
Specific Address 1 Top Register EMAC_SA1T Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
7
6
5
4 ADDR
3
2
1
0
* ADDR The most significant bits of the destination address, that is bits 47 to 32.
617
6120A-ATARM-01-Sep-05
40.5.18
Specific Address 2 Bottom Register EMAC_SA2B Read/Write
30 29 28 ADDR 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 ADDR
19
18
17
16
15
14
13
12 ADDR
11
10
9
8
7
6
5
4 ADDR
3
2
1
0
* ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.
40.5.19
Specific Address 2 Top Register EMAC_SA2T Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
7
6
5
4 ADDR
3
2
1
0
* ADDR The most significant bits of the destination address, that is bits 47 to 32.
618
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.20 Specific Address 3 Bottom Register EMAC_SA3B Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 40.5.21 Specific Address 3 Top Register EMAC_SA3T Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 7 6 5 4 ADDR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* ADDR The most significant bits of the destination address, that is bits 47 to 32.
619
6120A-ATARM-01-Sep-05
40.5.22
Specific Address 4 Bottom Register EMAC_SA4B Read/Write
30 29 28 ADDR 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 ADDR
19
18
17
16
15
14
13
12 ADDR
11
10
9
8
7
6
5
4 ADDR
3
2
1
0
* ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 40.5.23 Specific Address 4 Top Register EMAC_SA4T Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 7 6 5 4 ADDR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* ADDR The most significant bits of the destination address, that is bits 47 to 32.
620
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.24 Type ID Checking Register EMAC_TID Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TID 7 6 5 4 TID 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* TID: Type ID Checking For use in comparisons with received frames TypeID/Length field.
40.5.25
User Input/Output Register EMAC_USRIO Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 CLKEN 24 - 16 - 8 - 0 RMII
Register Name: Access Type:
31 - 23 - 15 - 7 -
* RMII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. * CLKEN When set, this bit enables the transceiver input clock. Setting this bit to 0 reduces power consumption when the treasurer is not used.
621
6120A-ATARM-01-Sep-05
40.5.26
EMAC Statistic Registers
These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 40.5.26.1 Pause Frames Received Register EMAC_PFR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 FROK 7 6 5 4 FROK 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* FROK: Pause Frames Received OK A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors.
40.5.26.2
Frames Transmitted OK Register EMAC_FTO Read/Write
30 - 22 29 - 21 28 - 20 FTOK 27 - 19 26 - 18 25 - 17 24 - 16
Register Name: Access Type:
31 - 23
15
14
13
12 FTOK
11
10
9
8
7
6
5
4 FTOK
3
2
1
0
* FTOK: Frames Transmitted OK A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
622
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.26.3 Single Collision Frames Register EMAC_SCF Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 SCF 7 6 5 4 SCF 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun.
40.5.26.4
Multicollision Frames Register EMAC_MCF Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 MCF 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
7
6
5
4 MCF
3
2
1
0
* MCF: Multicollision Frames A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.
623
6120A-ATARM-01-Sep-05
40.5.26.5
Frames Received OK Register EMAC_FRO Read/Write
30 - 22 29 - 21 28 - 20 FROK 27 - 19 26 - 18 25 - 17 24 - 16
Register Name: Access Type:
31 - 23
15
14
13
12 FROK
11
10
9
8
7
6
5
4 FROK
3
2
1
0
* FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory. A good frame is of length 64 to 1518 bytes (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors.
40.5.26.6
Frames Check Sequence Errors Register EMAC_FCSE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FCSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* FCSE: Frame Check Sequence Errors An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes.
624
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.26.7 Alignment Errors Register EMAC_ALE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 ALE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* ALE: Alignment Errors An 8-bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes.
40.5.26.8
Deferred Transmission Frames Register EMAC_DTF Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 DTF 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
7
6
5
4 DTF
3
2
1
0
* DTF: Deferred Transmission Frames A 16-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit underrun.
625
6120A-ATARM-01-Sep-05
40.5.26.9
Late Collisions Register EMAC_LCOL Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 LCOL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision.
40.5.26.10
Excessive Collisions Register EMAC_EXCOL Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 EXCOL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* EXCOL: Excessive Collisions An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.
626
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.26.11 Transmit Underrun Errors Register EMAC_TUND Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TUND 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented.
40.5.26.12
Carrier Sense Errors Register EMAC_CSE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* CSE: Carrier Sense Errors An 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no underrun). Only incremented in half-duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error.
627
6120A-ATARM-01-Sep-05
40.5.26.13
Receive Resource Errors Register EMAC_RRE Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RRE 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
7
6
5
4 RRE
3
2
1
0
* RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available.
40.5.26.14
Receive Overrun Errors Register EMAC_ROVR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 ROVR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* ROVR: Receive Overrun An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.
628
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.26.15 Receive Symbol Errors Register EMAC_RSE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception. Receive symbol errors are also counted as an FCS or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8 is set in the network configuration register). If the frame is larger, it is recorded as a jabber error.
40.5.26.16
Excessive Length Errors Register EMAC_ELE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 EXL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* EXL: Excessive Length Errors An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error.
629
6120A-ATARM-01-Sep-05
40.5.26.17
Receive Jabbers Register EMAC_RJA Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RJB 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.
40.5.26.18
Undersize Frames Register EMAC_USF Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 USF 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* USF: Undersize Frames An 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.
630
AT91SAM7X256/128 Preliminary
6120A-ATARM-01-Sep-05
AT91SAM7X256/128 Preliminary
40.5.26.19 SQE Test Errors Register EMAC_STE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 SQER 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* SQER: SQE Test Errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 40.5.26.20 Received Length Field Mismatch Register EMAC_RLE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RLFM 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* RLFM: Receive Length Field Mismatch An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. Checking is enabled through bit 16 of the network configuration register. Frames containing a type ID in bytes 13 and 14 (i.e., length/type ID 0x0600) are not counted as length field errors, neither are excessive length frames.
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41. AT91SAM7X256/128 Electrical Characteristics
41.1 Absolute Maximum Ratings
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 41-1.
Operating Temperature (Industrial).........-40 C to + 85 C Storage Temperature............................-60C to + 150C Voltage on Input Pins with Respect to Ground...........................-0.3V to + 5.5V Maximum Operating Voltage (VDDCORE, and VDDPLL)....................................1.95V Maximum Operating Voltage (VDDIO, VDDIN and VDDFLASH)............................3.6V Total DC Output Current on all I/O lines 100-lead LQFP package........................................200 mA
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41.2
DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a junction temperature up to TJ = 100C. Table 41-2.
Symbol VVDDCORE VVDDPLL VVDDIO VVDDFLASH VIL VIH VOL VOH
DC Characteristics
Parameter DC Supply Core DC Supply PLL DC Supply I/Os DC Supply Flash Input Low-level Voltage Input High-level Voltage Output Low-level Voltage Output High-level Voltage VVDDIO from 3.0V to 3.6V VVDDIO from 3.0V to 3.6V IO max, VVDDIO from 3.0V to 3.6V IO max, VVDDIO from 3.0V to 3.6V PA0-PA3, Pull-up resistors disabled (Typ: TA = 25C, Max: TA = 85C) Other PIOs, Pull-up resistors disabled (Typ: TA = 25C, Max: TA = 85C) PB27-PB30, VVDDIO from 3.0V to 3.6V, PAx connected to ground 10 143 135 VDDIO - 0.4 40 20 20.6 321 295 400 200 60 600 550 13.9 TA = 25C 12 60 A TA = 85C 100 400 Conditions Min 1.65 1.65 3.0 3.0 -0.3 2.0 Typ Max 1.95 1.95 3.6 3.6 0.8 5.5 0.4 Units V V V V V V V V nA nA A A A pF
ILEAK
Input Leakage Current
IPULLUP
Input Pull-up Current Other PIOs, VVDDIO from 3.0V to 3.6V, PAx connected to ground Input Pull-down Current, (TST, ERASE, JTAGSEL) Input Capacitance VVDDIO from 3.0V to 3.6V, Pins connected to VVDDIO 100 LQFP Package On VVDDCORE = 1.85V, MCK = 500Hz
IPULLDOWN CIN
ISC
Static Current (AT91SAM7X256/128)
All inputs driven at 1 (including TMS, TDI, TCK, NRST) Flash in standby mode All peripherals off PA0-PA3, VVDDIO from 3.0V to 3.6V
16 2 8 6
mA mA mA V/ms
IO
Output Current
PB27-PB30 and NRST, VVDDIO from 3.0V to 3.6V Other PIOs, VVDDIO from 3.0V to 3.6V
TSLOPE
Supply Core Slope
Note that even during startup, VVDDFLASH must always be superior or equal to VVDDCORE.
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Table 41-3.
Symbol VVDDIN VVDDOUT IVDDIN
1.8V Voltage Regulator Characteristics
Parameter Supply Voltage Output Voltage Current consumption IO = 20 mA After startup, no load After startup, Idle mode, no load Conditions Min 3.0 1.81 Typ 3.3 1.85 90 10 25 150 100 1 Max 3.6 1.89 Units V V A A S mA mA
TSTART IO IO
Startup Time Maximum DC Output Current Maximum DC Output Current
Cload = 2.2 F, after VDDIN > 2.7V VDDIN = 3.3V VDDIN = 3.3V, in Idle Mode
Table 41-4.
Symbol VBOT18VHYST18 VBOT33VHYST33 IDD TSTART
Brownout Detector Characteristics
Parameter VDDCORE Threshold Level VDDCORE Hysteresis VDDFLASH Threshold Level VDDFLASH Hysteresis Current Consumption BOD off (GPNVM0 bit inactive) Startup Time 100 1 200 A s VHYST33 = VBOT33+ - VBOT33BOD on (GPNVM0 bit active) VHYST18 = VBOT18+ - VBOT182.70 Conditions Min 1.65 Typ 1.68 50 2.80 70 24 Max 1.71 65 2.90 120 30 Units V mV V mV A
Table 41-5.
Symbol TPU
DC Flash Characteristics AT91SAM7X256/128
Parameter Power-up delay @25C onto VDDCORE = 1.8V onto VDDFLASH = 3.3V Conditions Min Max 45 10 30 10 120 3.0 0.8 400 5.5 Units S
A
ISB
Standby current @85C onto VDDCORE = 1.8V onto VDDFLASH = 3.3V Random Read @ 30MHz onto VDDCORE = 1.8V onto VDDFLASH = 3.3V A
mA
ICC
Active current Write onto VDDCORE = 1.8V onto VDDFLASH = 3.3V A mA
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41.3
Power Consumption
* Typical power consumption of PLLs, Slow Clock and Main Oscillator. * Power consumption of power supply in two different modes: Active and ultra Low-power. * Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock.
41.3.1
Power Consumption Versus Modes The values in Table 41-6 and Table 41-7 on page 637 are measured values of the power consumption with operating conditions as follows: * VDDIO = VDDIN = VDDFLASH= 3.3V * VDDCORE = VDDPLL = 1.85V * TA = 25 C * There is no consumption on the I/Os of the device Figure 41-1. Measure Schematics:
VDDFLASH
VDDIO
3.3V AMP1
VDDIN Voltage Regulator VDDOUT 1.8V
AMP2 VDDCORE
VDDPLL
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These figures represent the power consumption typically measured on the power supplies.. Table 41-6.
Mode
Power Consumption for Different Modes
Conditions Voltage regulator is on. Brown Out Detector is activated. Flash is read. ARM Core clock is 50MHz. Analog-to-Digital Converter activated. All peripheral clocks activated. USB transceiver enabled. onto AMP1 onto AMP2 Voltage regulator is in Low-power mode. Brown Out Detector is de-activated. Flash is in standby mode. ARM Core in idle mode. MCK @ 500Hz. Analog-to-Digital Converter de-activated. All peripheral clocks de-activated. USB transceiver disabled. DDM and DDP pins connected to ground. onto AMP1 onto AMP2 Consumption Unit
Active (AT91SAM7X256/128)
50 49
mA
Ultra low power
26 12
A
41.3.2
Peripheral Power Consumption in Active Mode Table 41-7.
Peripheral PIO Controller USART UDP PWM TWI SPI SSC Timer Counter Channels AES TDES CAN ARM7TDMI EMAC System Peripherals (AT91SAM7X128/256) Note: 1. Note: VDDCORE = 1.85V, TA = 25 C
Power Consumption on VDDCORE(1)
Consumption (Typ) 12 28 20 16 5 16 32 A/MHz 6 123 25 75 160 120 200 Unit
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41.4
41.4.1
Crystal Oscillators Characteristics
RC Oscillator Characteristics RC Oscillator Characteristics
Parameter RC Oscillator Frequency Duty Cycle Conditions VDDPLL = 1.65V Min 22 45 VDDPLL = 1.65V After Startup Time Typ 32 50 Max 42 55 75 1.9 Unit kHz % s A
Table 41-8.
Symbol 1/(tCPRC)
tST IOSC
Startup Time Current Consumption
41.4.2
Main Oscillator Characteristics Main Oscillator Characteristics
Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Equivalent Load Capacitance Duty Cycle VDDPLL = 1.2 to 2V CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz Active mode 40 Conditions Min 3 Typ 16 25 12.5 50 60 14.5 1.4 1 550 1 Max 20 Unit MHz pF pF %
Table 41-9.
Symbol 1/(tCPMAIN) CL1, CL2 CL
tST
Startup Time
ms
A A
IOSC Note:
Current Consumption Standby mode 1. CS is the shunt capacitance
41.4.3
XIN Clock Characteristics
Table 41-10. XIN Clock Electrical Characteristics
Symbol 1/(tCPXIN) tCPXIN tCHXIN tCLXIN CIN RIN VXIN_IL VXIN_IH Note: Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pull-down Resistor VXIN Input Low-level Voltage VXIN Input High-level Voltage Conditions
(1) (1) (1) (1) (1) (1) (1) (1)
Min
Max 50.0
Units MHz ns
20.0 0.4 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN 0.6 x tCPXIN 25 500 -0.3 0.8 x VDDPLL 0.2 x VDDPLL 1.95
pF k V V
1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register, see Section 26.9.7 "PMC Clock Generator Main Oscillator Register" on page 192.
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41.5 PLL Characteristics
Table 41-11. Phase Lock Loop Characteristics
Symbol FOUT FIN IPLL Note: Parameter Output Frequency Input Frequency Active mode Current Consumption Standby mode Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. 1 A Conditions 00 Field out of CKGR_PLL is: 10 150 1 220 32 4 MHz MHz mA Min 80 Typ Max 160 Unit MHz
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41.6
41.6.1
USB Transceiver Characteristics
Electrical Characteristics
Table 41-12. Electrical Parameters
Symbol Parameter Conditions Input Levels VIL VIH VDI VCM CIN I REXT Low Level High Level Differential Input Sensitivity Differential Input Common Mode Range Transceiver capacitance Hi-Z State Data Line Leakage Recommended External USB Series Resistor Capacitance to ground on each line 0V < VIN < 3.3V In series with each USB pin with 5% Output Levels VOL VOH VCRS Low Level Output High Level Output Output Signal Crossover Voltage Measured with RL of 1.425 kOhm tied to 3.6V Measured with RL of 14.25 kOhm tied to GND Measure conditions described in Figure 41-2 Consumption IVDDIO IVDDCORE Current Consumption Current Consumption Transceiver enabled in input mode DDP=1 and DDM=0 105 80 200 150 A A 0.0 2.8 1.3 0.3 3.6 2.0 V V V -10 27 |(D+) - (D-)| 2.0 0.2 0.8 2.5 9.18 +10 0.8 V V V V pF A Min Typ Max Unit
41.6.2
Switching Characteristics
Table 41-13. In Full Speed
Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 50 pF CLOAD = 50 pF Min 4 4 90 Typ Max 20 20 111.11 Unit ns ns %
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Figure 41-2. USB Data Signal Rise and Fall Times
Rise Time VCRS 10% Differential Data Lines tR (a) REXT=27 ohms Fosc = 6MHz/750kHz Buffer (b) Cload tF 90% 10% Fall Time
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41.7
ADC Characteristics
Table 41-14. Channel Conversion Time and ADC Clock
Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Conversion Time Throughput Rate Throughput Rate Notes: ADC Clock = 5 MHz ADC Clock = 8 MHz ADC Clock = 5 MHz ADC Clock = 8 MHz Conditions 10-bit resolution mode 8-bit resolution mode Return from Idle Mode 600 2 1.25 384
(1)
Min
Typ
Max 5 8 20
Units MHz MHz s ns s s kSPS kSPS
533(2)
1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. 2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
Table 41-15. External Voltage Reference Input
Parameter ADVREF Input Voltage Range ADVREF Average Current Current Consumption on VDDIN On 13 samples with ADC Clock = 5 MHz Conditions Min 2.6 200 0.55 Typ Max VDDIN 250 1 Units V A mA
Table 41-16. Analog Inputs
Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 1 12 14 Typ Max VADVREF A pF Units
The user can drive ADC input with impedance up to: * ZOUT (SHTIM -470) x 10 in 8-bit resolution mode * ZOUT (SHTIM -589) x 7.69 in 10-bit resolution mode with SHTIM (Sample and Hold Time register) expressed in ns and ZOUT expressed in ohms. Table 41-17. Transfer Characteristics
Parameter Resolution Integral Non-linearity Differential Non-linearity Offset Error Gain Error Min Typ 10 3 2 2 2 Max Units Bit LSB LSB LSB LSB
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41.8
41.8.1
AC Characteristics
Master Clock Characteristics
Table 41-18. Master Clock Waveform Parameters
Symbol 1/(tCPMCK) Parameter Master Clock Frequency Conditions Min Max 55 Units MHz
41.8.2
I/O Characteristics
Criteria used to define the maximum frequency of the I/Os: * output duty cycle (30%-70%) * minimum output swing: 100mV to VDDIO - 100mV * Addition of rising and falling time inferior to 75% of the period
Table 41-19. I/O Characteristics
Symbol FreqMaxI01 PulseminHI01 PulseminLI01 FreqMaxI02 Parameter Pin Group 1
(1)
Conditions frequency load: 40 pF
(4)
Min
Max 12.5 40 40 25 51 20 10 20 10 30
Units MHz ns ns MHz MHz ns ns ns ns MHz ns ns
Pin Group 1 (1) High Level Pulse Width Pin Group 1 (1) Low Level Pulse Width Pin Group 2 (2) frequency
load: 40 pF(4) load: 40 pF(4) load: 40 pF load: 20 pF
(4) (5)
PulseminHI02
Pin Group 2 (2) High Level Pulse Width
load: 40 pF(4) load: 20 pF(5) load: 40 pF load: 20 pF
(4) (5)
PulseminLI02 FreqMaxI03 PulseminHI03 PulseminLI03 Notes: 1. 2. 3. 4. 5.
Pin Group 2 (2) Low Level Pulse Width Pin Group 3 (3) frequency Pin Group 3 Pin Group 3
(3) (3)
load: 40 pF(4) load: 40 pF load: 40 pF
(4) (4)
High Level Pulse Width Low Level Pulse Width
16.6 16.6
Pin Group 1 = PB27 to PB30 Pin Group 2 = PA4 to PA30 and PB0 to PB30 Pin Group 3 = PA0 to PA3 VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20pF
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41.8.3
SPI Characteristics Figure 41-3. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
SPI0 MISO
SPI1
SPI2 MOSI
Figure 41-4. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
SPI3 MISO
SPI4
SPI5 MOSI
Figure 41-5. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
SPI6 MISO
SPI7 MOSI
SPI8
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Figure 41-6. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
SPI9 MISO
SPI10 MOSI
SPI11
Table 41-20. SPI Timings
Symbol SPI0 SPI1 SPI2 SPI3 SPI4 SPI5 SPI6 SPI7 SPI8 SPI9 SPI10 SPI11 Notes: Parameter MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) SPCK rising to MOSI Delay (master) MISO Setup time before SPCK falls (master) MISO Hold time after SPCK falls (master) SPCK falling to MOSI Delay (master) SPCK falling to MISO Delay (slave) MOSI Setup time before SPCK rises (slave) MOSI Hold time after SPCK rises (slave) SPCK rising to MISO Delay (slave) MOSI Setup time before SPCK falls (slave) MOSI Hold time after SPCK falls (slave) Conditions 3.3V domain
(1) (1) (1) (1) (1) (1)
Min
Max 28.5
Units ns ns
3.3V domain 3.3V domain
0 2 26.5 0 2 28 2 3 28 3 3
ns ns ns ns ns ns ns ns ns ns
3.3V domain 3.3V domain 3.3V domain
3.3V domain (1) 3.3V domain (1) 3.3V domain 3.3V domain 3.3V domain 3.3V domain
(1) (1) (1) (1)
1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF.
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41.8.4
Embedded Flash Characteristics
The maximum operating frequency is given in Table 41-21 but is limited by the Embedded Flash access time when the processor is fetching code out of it. Table 41-21 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory.
Table 41-21. Embedded Flash Wait States
FWS 0 1 2 3 Read Operations 1 cycle 2 cycles 3 cycles 4 cycles Maximum Operating Frequency (MHz) 30 55 55 55
Table 41-22. AC Flash Characteristics
Parameter Program Cycle Time per page without auto-erase Full Chip Erase 15 3 ms ms Conditions per page including auto-erase Min Max 6 Units ms
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41.8.5 41.8.5.1 JTAG/ICE Timings ICE Interface Signals
Table 41-23. ICE Interface Timing Specification
Symbol ICE0 ICE1 ICE2 ICE3 ICE4 ICE5 ICE6 Note: Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS, Setup before TCK High TDI, TMS, Hold after TCK High TDO Hold Time TCK Low to TDO Valid Conditions
(1) (1) (1) (1) (1) (1) (1)
Min 51 51 102 0 3 13
Max
Units ns ns ns ns ns ns 20 ns
1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF
Figure 41-7. ICE Interface Signals
ICE2 TCK ICE0 ICE1
TMS/TDI ICE3 ICE4
TDO ICE5 ICE6
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41.8.5.2
JTAG Interface Signals
Table 41-24. JTAG Interface Timing specification
Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Note: Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time TCK to Device Outputs Valid Conditions
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
Min 6.5 5.5 12 2 3 4
Max
Units ns ns ns ns ns ns
16 0 3 6 18
ns ns ns ns ns
1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF
Figure 41-8. JTAG Interface Signals
JTAG2 TCK JTAG JTAG1
0
TMS/TDI JTAG3 JTAG4
TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8
Device Outputs JTAG9 JTAG10
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42. AT91SAM7X256/128 Mechanical Characteristics
42.1
42.1.1
Thermal Considerations
Thermal Data Table 42-1 summarizes the thermal resistance data depending on the package. Table 42-1.
Symbol JA JC
Thermal Resistance Data
Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Condition Still Air Package LQFP100 LQFP100 Typ 38.3 8.7 Unit C/W
42.1.2
Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: 1. 2. T J = T A + ( P D x JA )
T J = T A + ( P D x ( HEATSINK + JC ) )
where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 42-1 on page 649. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 42-1 on page 649. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section Section 41.3 "Power Consumption" on page 636. * TA = ambient temperature (C).
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42.2
Package Drawings
Figure 42-1. LQFP Package Drawing
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Table 42-2.
Symbol A A1 A2 D D1 E E1 R2 R1 Q 1 2 3 c L L1 S b e D2 E2 aaa bbb ccc ddd 0.20 0.17 0.20 0.50 BSC 12.00 12.00 Tolerances of Form and Position 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.27 0.08 0.08 0 0 11 11 0.09 0.45 0.60 1.00 REF 0.008 0.007 0.008 0.020 BSC 0.472 0.472 0.011 12 12 13 13 0.20 0.75 3.5 7 0.05 1.35 1.40 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.20 0.003 0.003 0 0 11 11 0.004 0.018 0.024 0.039 REF 12 12 13 13 0.008 0.030 3.5 7
100-lead LQFP Package Dimensions
Millimeter Min Nom Max 1.60 0.15 1.45 0.002 0.053 0.055 0.630 BSC 0.551 BSC 0.630 BSC 0.551 BSC 0.008 Min Inch Nom Max 0.63 0.006 0.057
Table 42-3.
Device and LQFP Package Maximum Weight
800 mg
AT91SAM7X256/128
Table 42-4.
Package Reference
MS-026 e2
JEDEC Drawing Reference JESD97 Classification
Table 42-5.
LQFP Package Characteristics
3
Moisture Sensitivity Level
This package respects the recommendations of the NEMI User Group.
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42.3
Soldering Profile
Table 42-6 gives the recommended soldering profile from J-STD-020C. Table 42-6. Soldering Profile
Green Package 3 C/sec. max. 180 sec. max. 60 sec. to 150 sec. 20 sec. to 40 sec. 260 C 6 C/sec. max. 8 min. max.
Profile Feature Average Ramp-up Rate (217C to Peak) Preheat Temperature 175C 25C Temperature Maintained Above 217C Time within 5 C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25 C to Peak Temperature Note:
The package is certified to be backward compatible with Pb/Sn soldering profile.
A maximum of three reflow passes is allowed per component.
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43. AT91SAM7X256/128 Ordering Information
Table 43-1. Ordering Information
Package LQFP 100 LQFP 100 Package Type Green Green ROM Code Revision 001 001 Temperature Operating Range Industrial (-40 C to 85 C) Industrial (-40 C to 85 C)
Ordering Code AT91SAM7X256-AU-001 AT91SAM7X128-AU-001
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Table of Contents
Features ..................................................................................................... 1 1 2 3 4 5 Description ............................................................................................... 3 Configuration Summary of the AT91SAM7X256 and AT91SAM7X128 3 AT91SAM7X256/128 Block Diagram ....................................................... 4 Signal Description ................................................................................... 5 Package .................................................................................................... 8
5.1 5.2 100-lead LQFP Mechanical Overview ...................................................................8 AT91SAM7X256/128 Pinout .................................................................................8
6
Power Considerations ............................................................................. 9
6.1 6.2 6.3 6.4 Power Supplies .....................................................................................................9 Power Consumption ..............................................................................................9 Voltage Regulator ..................................................................................................9 Typical Powering Schematics .............................................................................10
7
I/O Lines Considerations ....................................................................... 11
7.1 7.2 7.3 7.4 7.5 7.6 JTAG Port Pins ....................................................................................................11 Test Pin ...............................................................................................................11 Reset Pin .............................................................................................................11 ERASE Pin ..........................................................................................................11 PIO Controller Lines ............................................................................................11 I/O Lines Current Drawing ...................................................................................12
8
Processor and Architecture .................................................................. 13
8.1 8.2 8.3 8.4 ARM7TDMI Processor ........................................................................................13 Debug and Test Features ....................................................................................13 Memory Controller ...............................................................................................13 Peripheral DMA Controller ..................................................................................14
9
Memory ................................................................................................... 15
9.1 9.2 9.3 9.4 9.5 AT91SAM7X256 ..................................................................................................15 AT91SAM7X128 ..................................................................................................15 Memory Mapping .................................................................................................16 Embedded Flash .................................................................................................17 Fast Flash Programming Interface ......................................................................19
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9.6
SAM-BA Boot Assistant .......................................................................................19
10 System Controller .................................................................................. 20
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 System Controller Mapping ...............................................................................21 Reset Controller ................................................................................................22 Clock Generator ................................................................................................23 Power Management Controller ..........................................................................24 Advanced Interrupt Controller ...........................................................................24 Debug Unit ........................................................................................................25 Period Interval Timer .........................................................................................25 Watchdog Timer ................................................................................................25 Real-time Timer .................................................................................................25 PIO Controllers ................................................................................................26 Voltage Regulator Controller ...........................................................................26
11 Peripherals ............................................................................................. 27
11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 Peripheral Mapping ...........................................................................................27 Peripheral Multiplexing on PIO Lines ................................................................28 PIO Controller A Multiplexing ............................................................................29 PIO Controller B Multiplexing ............................................................................30 Peripheral Identifiers .........................................................................................31 Ethernet MAC ....................................................................................................32 Serial Peripheral Interface .................................................................................32 Two-wire Interface .............................................................................................32 USART ..............................................................................................................33 Serial Synchronous Controller .........................................................................33 Timer Counter .................................................................................................33 Pulse Width Modulation Controller ..................................................................34 USB Device Port .............................................................................................34 CAN Controller ................................................................................................35 128-bit Advanced Encryption Standard ...........................................................35 Triple Data Encryption Standard .....................................................................35 Analog-to-Digital Converter .............................................................................36
12 ARM7TDMI Processor Overview .......................................................... 37
12.1 12.2 Overview ...........................................................................................................37 ARM7TDMI Processor ......................................................................................38
13 Debug and Test Features ...................................................................... 43
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13.1 13.2 13.3 13.4 13.5 Description ........................................................................................................43 Block Diagram ...................................................................................................43 Application Examples ........................................................................................44 Debug and Test Pin Description ........................................................................45 Functional Description .......................................................................................46
14 Reset Controller (RSTC) ........................................................................ 55
14.1 14.2 14.3 14.4 Overview ...........................................................................................................55 Block Diagram ...................................................................................................55 Functional Description .......................................................................................56 Reset Controller (RSTC) User Interface ............................................................65
15 Real-time Timer (RTT) ............................................................................ 69
15.1 15.2 15.3 15.4 Overview ...........................................................................................................69 Block Diagram ...................................................................................................69 Functional Description .......................................................................................69 Real-time Timer (RTT) User Interface ...............................................................71
16 Periodic Interval Timer (PIT) ................................................................. 75
16.1 16.2 16.3 16.4 Overview ...........................................................................................................75 Block Diagram ...................................................................................................75 Functional Description .......................................................................................76 Periodic Interval Timer (PIT) User Interface ......................................................78
17 Watchdog Timer (WDT) ......................................................................... 81
17.1 17.2 17.3 17.4 Overview ...........................................................................................................81 Block Diagram ...................................................................................................81 Functional Description .......................................................................................82 Watchdog Timer (WDT) User Interface .............................................................84
18 Voltage Regulator Mode Controller (VREG) ........................................ 87
18.1 18.2 Overview ...........................................................................................................87 Voltage Regulator Power Controller (VREG) User Interface .............................88
19 Memory Controller (MC) ........................................................................ 89
19.1 19.2 19.3 19.4 Overview ...........................................................................................................89 Block Diagram ...................................................................................................89 Functional Description .......................................................................................90 Memory Controller (MC) User Interface ............................................................94
20 Embedded Flash Controller (EFC) ....................................................... 99
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20.1 20.2
Functional Description .......................................................................................99 Embedded Flash Controller (EFC) User Interface ...........................................109
21 Fast Flash Programming Interface (FFPI) .......................................... 115
21.1 21.2 21.3 Overview .........................................................................................................115 Parallel Fast Flash Programming ....................................................................115 Serial Fast Flash Programming .......................................................................125
22 AT91SAM Boot Program ..................................................................... 133
22.1 22.2 22.3 22.4 22.5 Description ......................................................................................................133 Flow Diagram ..................................................................................................133 Device Initialization ..........................................................................................133 SAM-BA Boot ..................................................................................................133 Hardware and Software Constraints ...............................................................137
23 Peripheral DMA Controller (PDC) ....................................................... 139
23.1 23.2 23.3 23.4 Overview .........................................................................................................139 Block Diagram .................................................................................................139 Functional Description .....................................................................................140 Peripheral DMA Controller (PDC) User Interface ............................................142
24 Advanced Interrupt Controller (AIC) .................................................. 149
24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 Overview .........................................................................................................149 Block Diagram .................................................................................................149 Application Block Diagram ..............................................................................149 AIC Detailed Block Diagram ............................................................................150 I/O Line Description .........................................................................................150 Product Dependencies ....................................................................................150 Functional Description .....................................................................................152 Advanced Interrupt Controller (AIC) User Interface .........................................162
25 Clock Generator ................................................................................... 173
25.1 25.2 25.3 25.4 Description ......................................................................................................173 Slow Clock RC Oscillator .................................................................................173 Main Oscillator .................................................................................................173 Divider and PLL Block .....................................................................................175
26 Power Management Controller (PMC) ................................................ 177
26.1 26.2 Description ......................................................................................................177 Master Clock Controller ...................................................................................177
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26.3 26.4 26.5 26.6 26.7 26.8 26.9 Processor Clock Controller ..............................................................................178 USB Clock Controller ......................................................................................178 Peripheral Clock Controller .............................................................................178 Programmable Clock Output Controller ...........................................................179 Programming Sequence ..................................................................................179 Clock Switching Details ...................................................................................183 Power Management Controller (PMC) User Interface ....................................186
27 Debug Unit (DBGU) .............................................................................. 201
27.1 27.2 27.3 27.4 27.5 Overview .........................................................................................................201 Block Diagram .................................................................................................202 Product Dependencies ....................................................................................203 UART Operations ............................................................................................204 Debug Unit User Interface ..............................................................................211
28 Parallel Input/Output Controller (PIO) ................................................ 225
28.1 28.2 28.3 28.4 28.5 28.6 28.7 Overview .........................................................................................................225 Block Diagram .................................................................................................226 Application Block Diagram ..............................................................................226 Product Dependencies ....................................................................................227 Functional Description .....................................................................................228 I/O Lines Programming Example ....................................................................233 Parallel Input/Output Controller (PIO) User Interface ......................................234
29 Serial Peripheral Interface (SPI) ......................................................... 251
29.1 29.2 29.3 29.4 29.5 29.6 29.7 Overview .........................................................................................................251 Block Diagram .................................................................................................252 Application Block Diagram ..............................................................................252 Signal Description ...........................................................................................253 Product Dependencies ....................................................................................253 Functional Description .....................................................................................254 Serial Peripheral Interface (SPI) User Interface .............................................263
30 Two-wire Interface (TWI) ..................................................................... 277
30.1 30.2 30.3 30.4 30.5 Overview .........................................................................................................277 Block Diagram .................................................................................................277 Application Block Diagram ..............................................................................277 Product Dependencies ....................................................................................278 Functional Description .....................................................................................279 v
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30.6
Two-wire Interface (TWI) User Interface ........................................................284
31 Universal Synchronous Asynchronous Receiver Transmitter (USART) 293
31.1 31.2 31.3 31.4 31.5 31.6 31.7 Overview .........................................................................................................293 Block Diagram .................................................................................................294 Application Block Diagram ..............................................................................295 I/O Lines Description ......................................................................................295 Product Dependencies ....................................................................................296 Functional Description .....................................................................................297 USART User Interface ....................................................................................328
32 Synchronous Serial Controller (SSC) ................................................ 347
32.1 32.2 32.3 32.4 32.5 32.6 32.7 32.8 Overview .........................................................................................................347 Block Diagram .................................................................................................348 Application Block Diagram ..............................................................................348 Pin Name List ..................................................................................................349 Product Dependencies ....................................................................................349 Functional Description .....................................................................................349 SSC Application Examples ..............................................................................360 Synchronous Serial Controller (SSC) User Interface ......................................362
33 Timer/Counter (TC) .............................................................................. 385
33.1 33.2 33.3 33.4 33.5 33.6 Overview .........................................................................................................385 Block Diagram .................................................................................................385 Pin Name List ..................................................................................................386 Product Dependencies ....................................................................................386 Functional Description .....................................................................................387 Timer/Counter (TC) User Interface ..................................................................400
34 Pulse Width Modulation Controller (PWM) ........................................ 419
34.1 34.2 34.3 34.4 34.5 34.6 Overview .........................................................................................................419 Block Diagram .................................................................................................419 I/O Lines Description .......................................................................................420 Product Dependencies ....................................................................................420 Functional Description .....................................................................................421 Pulse Width Modulation Controller (PWM) User Interface ..............................429
35 USB Device Port (UDP) ........................................................................ 439
35.1 vi Description ......................................................................................................439
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35.2 35.3 35.4 35.5 35.6 Block Diagram .................................................................................................440 Product Dependencies ....................................................................................440 Typical Connection ..........................................................................................442 Functional Description .....................................................................................443 USB Device Port (UDP) User Interface ...........................................................457
36 Analog-to-digital Converter (ADC) ..................................................... 475
36.1 36.2 36.3 36.4 36.5 36.6 Overview .........................................................................................................475 Block Diagram .................................................................................................475 Signal Description ...........................................................................................476 Product Dependencies ....................................................................................476 Functional Description .....................................................................................477 Analog-to-digital Converter (ADC) User Interface ...........................................481
37 Advanced Encryption Standard (AES) ............................................... 491
37.1 37.2 37.3 37.4 Overview .........................................................................................................491 Product Dependencies ....................................................................................491 Functional Description .....................................................................................492 Advanced Encryption Standard (AES) User Interface .....................................498
38 Triple Data Encryption System (TDES) .............................................. 509
38.1 38.2 38.3 38.4 Description ......................................................................................................509 Product Dependencies ....................................................................................509 Functional Description .....................................................................................510 Triple DES (TDES) User Interface ...................................................................516
39 Controller Area Network (CAN) .......................................................... 529
39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 Description ......................................................................................................529 Block Diagram .................................................................................................530 Application Block Diagram ..............................................................................531 I/O Lines Description ......................................................................................531 Product Dependencies ....................................................................................531 CAN Controller Features .................................................................................532 Functional Description .....................................................................................544 Controller Area Network (CAN) User Interface ...............................................557
40 Ethernet MAC 10/100 (EMAC) ............................................................. 585
40.1 40.2 Overview .........................................................................................................585 Block Diagram .................................................................................................585
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40.3 40.4 40.5
Functional Description .....................................................................................586 Programming Interface ....................................................................................597 Ethernet MAC 10/100 (EMAC) User Interface .................................................600
41 AT91SAM7X256/128 Electrical Characteristics ................................. 633
41.1 41.2 41.3 41.4 41.5 41.6 41.7 41.8 Absolute Maximum Ratings .............................................................................633 DC Characteristics ..........................................................................................634 Power Consumption ........................................................................................636 Crystal Oscillators Characteristics ...................................................................638 PLL Characteristics .........................................................................................639 USB Transceiver Characteristics .....................................................................640 ADC Characteristics .......................................................................................642 AC Characteristics ...........................................................................................643
42 Mechanical Characteristics ................................................................. 649
42.1 42.2 42.3 Thermal Considerations ..................................................................................649 Package Drawings ..........................................................................................650 Soldering Profile ..............................................................................................652
43 AT91SAM7X256/128 Ordering Information ........................................ 653 Table of Contents...................................................................................... i Revision History....................................................................................... ix
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Revision History
Doc. Rev. 6120A
Date 01-Sep-05
Comments First issue.
Change Request Ref.
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